docs: restructuring images directory

see also previous commit
Also updates `scripting_intro.rst` to use literal includes, and uses individual image outputs to avoid the intermediary `.tex` file to join them all.

docs/.gitignore

@@ -1,12 +1,9 @@
 /build/
 /source/cmd
 /source/temp
-/source/_images/*.log
-/source/_images/*.aux
-/source/_images/*.pdf
-/source/_images/*.svg
 /source/_images/**/*.log
 /source/_images/**/*.aux
 /source/_images/**/*.pdf
 /source/_images/**/*.svg
 /source/_images/**/*.dot
+/source/_images/code_examples

docs/source/_images/011/example_out.tex

@@ -1,18 +0,0 @@
-\documentclass[12pt,tikz]{standalone}
-\pdfinfoomitdate 1
-\pdfsuppressptexinfo 1
-\pdftrailerid{}
-\usepackage[utf8]{inputenc}
-\usepackage{tikz}
-\pagestyle{empty}
-
-\begin{document}
-\begin{tikzpicture}
-	\node[inner sep=0pt] at (0,0)
-		{\includegraphics[width=\linewidth]{example_00.pdf}};
-	\node[inner sep=0pt] at (0,-3.8)
-		{\includegraphics[width=\linewidth]{example_01.pdf}};
-	\node[inner sep=0pt] at (0,-7)
-		{\includegraphics[width=\linewidth]{example_02.pdf}};
-\end{tikzpicture}
-\end{document}

docs/source/_images/011/select_prod.tex

@@ -1,19 +0,0 @@
-\documentclass[12pt,tikz]{standalone}
-\pdfinfoomitdate 1
-\pdfsuppressptexinfo 1
-\pdftrailerid{}
-\usepackage[utf8]{inputenc}
-\pagestyle{empty}
-
-\begin{document}
-\begin{tikzpicture}
-	\node[inner sep=0pt] at (0,0)
-		{\hfill \includegraphics[width=4cm,trim=0 1cm 0 1cm]{sumprod_02.pdf}};
-	\node[inner sep=0pt] at (0,-2.8)
-		{\includegraphics[width=\linewidth,trim=0 0cm 0 1cm]{sumprod_03.pdf}};
-	\node[inner sep=0pt] at (0,-6.2)
-		{\includegraphics[width=\linewidth,trim=0 0cm 0 1cm]{sumprod_04.pdf}};
-	\node[inner sep=0pt] at (0,-9.2)
-		{\includegraphics[width=\linewidth,trim=0 1cm 0 1cm]{sumprod_05.pdf}};
-\end{tikzpicture}
-\end{document}

docs/source/_images/011/splitnets_libfile.tex

@@ -1,15 +0,0 @@
-\documentclass[12pt,tikz]{standalone}
-\pdfinfoomitdate 1
-\pdfsuppressptexinfo 1
-\pdftrailerid{}
-\usepackage[utf8]{inputenc}
-\pagestyle{empty}
-
-\begin{document}
-\begin{tikzpicture}
-	\node[inner sep=0pt] at (0,0)
-		{\includegraphics[height=\linewidth]{cmos_00.pdf}};
-	\node[inner sep=0pt] at (2,-8)
-		{\includegraphics[width=\linewidth]{cmos_01.pdf}};
-\end{tikzpicture}
-\end{document}

docs/source/_images/011/submod_dots.tex

@@ -1,27 +0,0 @@
-\documentclass[12pt,tikz]{standalone}
-\pdfinfoomitdate 1
-\pdfsuppressptexinfo 1
-\pdftrailerid{}
-\usepackage[utf8]{inputenc}
-\pagestyle{empty}
-
-\begin{document}
-\begin{tikzpicture}
-	\node[inner sep=0pt] at (0,0)
-		{\includegraphics[width=\linewidth,trim=0 1.3cm 0 0cm]{submod_00.pdf}};
-	\node at (0, -2.5)
-		{\tt memdemo};
-	\node[inner sep=0pt] at (0,-5)
-		{\includegraphics[width=\linewidth,trim=0 1.3cm 0 0cm]{submod_01.pdf}};
-	\node at (0, -7.5)
-		{\tt scramble};
-	\node[inner sep=0pt] at (0, -11)
-		{\includegraphics[width=\linewidth,trim=0 1.3cm 0 0cm]{submod_02.pdf}};
-	\node at (0, -14.8)
-		{\tt outstage};
-	\node[inner sep=0pt] at (0,-16.6)
-		{\includegraphics[width=\linewidth,trim=0 1.3cm 0 0cm]{submod_03.pdf}};
-	\node at (0, -19)
-		{\tt selstage};
-\end{tikzpicture}
-\end{document}

docs/source/_images/Makefile

@@ -1,62 +1,46 @@
-all: resources dots tex svg tidy
+all: examples all_tex tidy
 
-RES_LIST:= PRESENTATION_Intro/ PRESENTATION_ExSyn/ PRESENTATION_ExAdv/ PRESENTATION_ExOth/
-RES_DIRS:= $(addprefix ../../resources/,$(RES_LIST))
-.PHONY: resources
-resources: $(RES_DIRS)
+# set a fake time in pdf generation to prevent unnecessary differences in output
+FAKETIME := TZ='Z' faketime -f '2022-01-01 00:00:00 x0,001'
+
+# find all code example makefiles
+.PHONY: examples
+CODE_EXAMPLES := ../code_examples/*/Makefile
+examples: $(CODE_EXAMPLES)
+
+# target to convert specified dot file(s)
+.PHONY: convert
+TARG_DOT ?=
+convert: $(TARG_DOT:.dot=.pdf) $(TARG_DOT:.dot=.svg)
+
+# use empty FORCE target because .PHONY ignores % expansion, using find allows
+# us to generate everything in one pass, since we don't know all of the possible
+# outputs until the sub-makes run
 FORCE:
-../../resources/%: FORCE
-	@$(MAKE) -C $@
-	@mkdir -p res/$*
-	@cp --update -t res/$* $@*.dot
+../%/Makefile: FORCE
+	@make -C $(@D) dots
+	@mkdir -p $*
+	@find $(@D) -name *.dot -exec cp -u {} -t $* \;
+	@find $* -name *.dot -printf "%p " | xargs -i make --no-print-directory convert TARG_DOT="{}"
 
-TEX_SOURCE:= $(wildcard *.tex)
-DOT_LOC:= ../APPNOTE_011_Design_Investigation
-DOT_SOURCE:= $(wildcard $(DOT_LOC)/*.dot)
+# find and build all tex files
+.PHONY: all_tex
+TEX_FILES := $(wildcard **/*.tex)
+all_tex: $(TEX_FILES:.tex=.pdf) $(TEX_FILES:.tex=.svg)
 
-RES_DOTS:= $(wildcard res/*/*.dot)
-RES_DIRS:= $(sort $(dir $(RES_DOTS)))
-RES_PDF:= $(RES_DOTS:%.dot=%.pdf)
-
-TEX_SOURCE+= 011/example_out.tex
-011/example_out.pdf: 011/example_00.pdf 011/example_01.pdf 011/example_02.pdf
-TEX_SOURCE+= 011/select_prod.tex
-011/select_prod.pdf: 011/sumprod_02.pdf 011/sumprod_03.pdf 011/sumprod_04.pdf 011/sumprod_05.pdf
-TEX_SOURCE+= 011/splitnets_libfile.tex
-011/splitnets_libfile.pdf: 011/cmos_00.pdf 011/cmos_01.pdf
-TEX_SOURCE+= 011/submod_dots.tex
-011/submod_dots.pdf: 011/submod_00.pdf 011/submod_01.pdf 011/submod_02.pdf 011/submod_03.pdf
-
-TEX_PDF:= $(patsubst %.tex,%.pdf,$(TEX_SOURCE))
-DOT_PDF:= $(addprefix 011/,$(notdir $(patsubst %.dot,%.pdf,$(DOT_SOURCE))))
-SVG_OUTPUT:= $(patsubst %.pdf,%.svg,$(TEX_PDF) $(DOT_PDF) $(RES_PDF))
-
-dots: $(DOT_PDF) $(RES_PDF)
-tex: $(TEX_PDF)
-svg: $(SVG_OUTPUT)
-
-011/%.pdf: $(DOT_LOC)/%.dot
-	TZ='Z' faketime -f '2022-01-01 00:00:00 x0,001' dot -Tpdf -o $@ $<
-
-res/%.pdf: res/%.dot
-	TZ='Z' faketime -f '2022-01-01 00:00:00 x0,001' dot -Tpdf -o $@ $<
-
-011/%.pdf: 011/%.tex
-	cd 011 && TZ='Z' faketime -f '2022-01-01 00:00:00 x0,001' pdflatex $(<F) --interaction=nonstopmode
+%.pdf: %.dot
+	$(FAKETIME) dot -Tpdf -o $@ $<
 
 %.pdf: %.tex
-	pdflatex $< --interaction=nonstopmode
+	cd $(@D) && $(FAKETIME) pdflatex $(<F) --interaction=nonstopmode
 
 %.svg: %.pdf
 	pdf2svg $< $@
 
 .PHONY: clean tidy
 tidy:
-	rm -f *.log
-	rm -f *.aux
-	rm -f  011/*.log 011/*.aux
+	rm -f  **/*.log **/*.aux
+
 clean: tidy
-	rm -f *.pdf
-	rm -f *.svg
-	rm -f 011/*.pdf 011/*.svg
-	rm -rf $(RES_DIRS)
+	rm -rf code_examples
+	rm -f **/*.pdf **/*.svg

docs/source/appendix/primer.rst

@@ -23,7 +23,7 @@ circuit to a functionally equivalent low-level representation of a circuit.
 :numref:`Figure %s <fig:Basics_abstractions>` lists the different levels of
 abstraction and how they relate to different kinds of synthesis.
 
-.. figure:: /_images/basics_abstractions.*
+.. figure:: /_images/primer/basics_abstractions.*
 	:class: width-helper
 	:name: fig:Basics_abstractions
 
@@ -498,7 +498,7 @@ Then the synthesizable description is transformed to lower-level representations
 using a series of tools and the results are again verified using simulation.
 This process is illustrated in :numref:`Fig. %s <fig:Basics_flow>`.
 
-.. figure:: /_images/basics_flow.*
+.. figure:: /_images/primer/basics_flow.*
 	:class: width-helper
 	:name: fig:Basics_flow
 
@@ -597,7 +597,7 @@ Let's consider the following BNF (in Bison syntax):
    assign_stmt: TOK_ASSIGN TOK_IDENTIFIER TOK_EQ expr TOK_SEMICOLON;
    expr: TOK_IDENTIFIER | TOK_NUMBER | expr TOK_PLUS expr;
 
-.. figure:: /_images/basics_parsetree.*
+.. figure:: /_images/primer/basics_parsetree.*
 	:class: width-helper
 	:name: fig:Basics_parsetree
 
@@ -626,7 +626,7 @@ Usually the AST is then converted into yet another representation that is more
 suitable for further processing. In compilers this is often an assembler-like
 three-address-code intermediate representation. :cite:p:`Dragonbook`
 
-.. figure:: /_images/basics_ast.*
+.. figure:: /_images/primer/basics_ast.*
 	:class: width-helper
 	:name: fig:Basics_ast
 

docs/source/code_examples/intro/Makefile

@@ -1,13 +1,10 @@
 PROGRAM_PREFIX :=
 
-YOSYS ?= ../../../$(PROGRAM_PREFIX)yosys
+YOSYS ?= ../../../../$(PROGRAM_PREFIX)yosys
 
-all: counter_00.dot counter_01.dot counter_02.dot counter_03.dot
+DOTS = counter_00.dot counter_01.dot counter_02.dot counter_03.dot
 
-counter_00.dot: counter.v counter.ys mycells.lib
+dots: $(DOTS)
+
+$(DOTS): counter.v counter.ys mycells.lib
 	$(YOSYS) counter_outputs.ys
-
-counter_01.dot: counter_00.dot
-counter_02.dot: counter_00.dot
-counter_03.dot: counter_00.dot
-

docs/source/code_examples/macc/Makefile

@@ -1,12 +1,14 @@
 PROGRAM_PREFIX :=
 
-YOSYS ?= ../../../$(PROGRAM_PREFIX)yosys
+YOSYS ?= ../../../../$(PROGRAM_PREFIX)yosys
 
-all: macc_simple_xmap.pdf macc_xilinx_xmap.pdf
+DOTS = macc_simple_xmap.dot macc_xilinx_xmap.dot
 
-macc_simple_xmap.pdf: macc_simple_*.v macc_simple_test.ys
+dots: $(DOTS)
+
+macc_simple_xmap.dot: macc_simple_*.v macc_simple_test.ys
 	$(YOSYS) macc_simple_test.ys
 
-macc_xilinx_xmap.pdf: macc_xilinx_*.v macc_xilinx_test.ys
+macc_xilinx_xmap.dot: macc_xilinx_*.v macc_xilinx_test.ys
 	$(YOSYS) macc_xilinx_test.ys
 

docs/source/code_examples/macc/macc_xilinx_test.ys

@@ -3,21 +3,21 @@ read_verilog -lib -icells macc_xilinx_unwrap_map.v
 read_verilog -lib -icells macc_xilinx_xmap.v
 hierarchy -check ;;
 
-show -prefix macc_xilinx_test1a -format pdf -notitle test1
-show -prefix macc_xilinx_test2a -format pdf -notitle test2
+show -prefix macc_xilinx_test1a -format dot -notitle test1
+show -prefix macc_xilinx_test2a -format dot -notitle test2
 
 techmap -map macc_xilinx_swap_map.v;;
 
-show -prefix macc_xilinx_test1b -format pdf -notitle test1
-show -prefix macc_xilinx_test2b -format pdf -notitle test2
+show -prefix macc_xilinx_test1b -format dot -notitle test1
+show -prefix macc_xilinx_test2b -format dot -notitle test2
 
 techmap -map macc_xilinx_wrap_map.v
 
 connwrappers -unsigned $__mul_wrapper Y Y_WIDTH \
              -unsigned $__add_wrapper Y Y_WIDTH;;
 
-show -prefix macc_xilinx_test1c -format pdf -notitle test1
-show -prefix macc_xilinx_test2c -format pdf -notitle test2
+show -prefix macc_xilinx_test1c -format dot -notitle test1
+show -prefix macc_xilinx_test2c -format dot -notitle test2
 
 design -push
 read_verilog macc_xilinx_xmap.v
@@ -30,14 +30,14 @@ extract -constports -ignore_parameters \
         -map %__macc_xilinx_xmap       \
         -swap $__add_wrapper A,B ;;
 
-show -prefix macc_xilinx_test1d -format pdf -notitle test1
-show -prefix macc_xilinx_test2d -format pdf -notitle test2
+show -prefix macc_xilinx_test1d -format dot -notitle test1
+show -prefix macc_xilinx_test2d -format dot -notitle test2
 
 techmap -map macc_xilinx_unwrap_map.v;;
 
-show -prefix macc_xilinx_test1e -format pdf -notitle test1
-show -prefix macc_xilinx_test2e -format pdf -notitle test2
+show -prefix macc_xilinx_test1e -format dot -notitle test1
+show -prefix macc_xilinx_test2e -format dot -notitle test2
 
 design -load __macc_xilinx_xmap
-show -prefix macc_xilinx_xmap -format pdf -notitle
+show -prefix macc_xilinx_xmap -format dot -notitle
 

docs/source/code_examples/scrambler/Makefile

@@ -1,8 +1,8 @@
 PROGRAM_PREFIX :=
 
-YOSYS ?= ../../../$(PROGRAM_PREFIX)yosys
+YOSYS ?= ../../../../$(PROGRAM_PREFIX)yosys
 
-all: scrambler_p01.dot scrambler_p02.dot
+dots: scrambler_p01.dot scrambler_p02.dot
 
 scrambler_p01.dot scrambler_p02.dot: scrambler.ys scrambler.v
 	$(YOSYS) scrambler.ys

docs/source/code_examples/selections/Makefile

@@ -11,22 +11,22 @@ MEMDEMO_DOTS := $(addsuffix .dot,$(MEMDEMO))
 SUBMOD = submod_00 submod_01 submod_02 submod_03
 SUBMOD_DOTS := $(addsuffix .dot,$(SUBMOD))
 
-all: select.dot $(SUMPROD_DOTS) $(MEMDEMO_DOTS)
+dots: select.dot $(SUMPROD_DOTS) $(MEMDEMO_DOTS) $(SUBMOD_DOTS)
 
 select.dot: select.v select.ys
 	$(YOSYS) select.ys
 
 $(SUMPROD_DOTS): sumprod.v
-	$(YOSYS) -p 'opt; cd sumprod; select a:sumstuff; show -format dot -prefix sumprod_00' sumprod.v
-	$(YOSYS) -p 'opt; cd sumprod; select a:sumstuff %x; show -format dot -prefix sumprod_01' sumprod.v
-	$(YOSYS) -p 'opt; cd sumprod; select prod; show -format dot -prefix sumprod_02' sumprod.v
-	$(YOSYS) -p 'opt; cd sumprod; select prod %ci; show -format dot -prefix sumprod_03' sumprod.v
-	$(YOSYS) -p 'opt; cd sumprod; select prod %ci2; show -format dot -prefix sumprod_04' sumprod.v
-	$(YOSYS) -p 'opt; cd sumprod; select prod %ci3; show -format dot -prefix sumprod_05' sumprod.v
+	$(YOSYS) -p 'read_verilog sumprod.v; opt; cd sumprod; select a:sumstuff; show -format dot -prefix sumprod_00'
+	$(YOSYS) -p 'read_verilog sumprod.v; opt; cd sumprod; select a:sumstuff %x; show -format dot -prefix sumprod_01'
+	$(YOSYS) -p 'read_verilog sumprod.v; opt; cd sumprod; select prod; show -format dot -prefix sumprod_02'
+	$(YOSYS) -p 'read_verilog sumprod.v; opt; cd sumprod; select prod %ci; show -format dot -prefix sumprod_03'
+	$(YOSYS) -p 'read_verilog sumprod.v; opt; cd sumprod; select prod %ci2; show -format dot -prefix sumprod_04'
+	$(YOSYS) -p 'read_verilog sumprod.v; opt; cd sumprod; select prod %ci3; show -format dot -prefix sumprod_05'
 
 $(MEMDEMO_DOTS): memdemo.v
-	$(YOSYS) -p 'proc; opt; memory; opt; cd memdemo; show -format dot -prefix memdemo_00' memdemo.v
-	$(YOSYS) -p 'proc; opt; memory; opt; cd memdemo; show -format dot -prefix memdemo_01 y %ci2:+$dff[Q,D] %ci*:-$mux[S]:-$dff' memdemo.v
+	$(YOSYS) -p 'read_verilog memdemo.v; proc; opt; memory; opt; cd memdemo; show -format dot -prefix memdemo_00'
+	$(YOSYS) -p 'read_verilog memdemo.v; proc; opt; memory; opt; cd memdemo; show -format dot -prefix memdemo_01 y %ci2:+$dff[Q,D] %ci*:-$mux[S]:-$dff'
 
 $(SUBMOD_DOTS): submod.ys memdemo.v
 	$(YOSYS) submod.ys

docs/source/code_examples/show/Makefile

@@ -2,16 +2,16 @@ PROGRAM_PREFIX :=
 
 YOSYS ?= ../../../../$(PROGRAM_PREFIX)yosys
 
-EXAMPLE = example_00 example_01 example_02 example_03
+EXAMPLE = example_00 example_01 example_02
 EXAMPLE_DOTS := $(addsuffix .dot,$(EXAMPLE))
 
 CMOS = cmos_00 cmos_01
 CMOS_DOTS := $(addsuffix .dot,$(CMOS))
 
-all: splice.dot $(EXAMPLE_DOTS) $(CMOS_DOTS)
+dots: splice.dot $(EXAMPLE_DOTS) $(CMOS_DOTS)
 
 splice.dot: splice.v
-	$(YOSYS) -p 'proc; opt; show -format dot -prefix splice' splice.v
+	$(YOSYS) -p 'read_verilog splice.v; proc; opt; show -format dot -prefix splice'
 
 $(EXAMPLE_DOTS): example.v example.ys
 	$(YOSYS) example.ys

docs/source/code_examples/show/example.ys

@@ -4,8 +4,3 @@ proc
 show -format dot -prefix example_01
 opt
 show -format dot -prefix example_02
-
-cd example
-select t:$add
-show -format dot -prefix example_03
-

docs/source/code_examples/stubnets/Makefile

@@ -1,3 +1,5 @@
+dots:
+
 test: stubnets.so
 	yosys -ql test1.log -m ./stubnets.so test.v -p "stubnets"
 	yosys -ql test2.log -m ./stubnets.so test.v -p "opt; stubnets"

docs/source/code_examples/synth_flow/Makefile

@@ -7,18 +7,15 @@ TARGETS += abc_01
 
 PROGRAM_PREFIX :=
 
-YOSYS ?= ../../../$(PROGRAM_PREFIX)yosys
+YOSYS ?= ../../../../$(PROGRAM_PREFIX)yosys
 
-all: $(addsuffix .pdf,$(TARGETS))
+DOTS = $(addsuffix .dot,$(TARGETS))
 
-define make_pdf_template
-$(1).pdf: $(1)*.v $(1)*.ys
-	$(YOSYS) -p 'script $(1).ys; show -notitle -prefix $(1) -format pdf'
-endef
+dots: $(DOTS)
 
-$(foreach trg,$(TARGETS),$(eval $(call make_pdf_template,$(trg))))
+%.dot: %.v %.ys
+	$(YOSYS) -p 'script $*.ys; show -notitle -prefix $* -format dot'
 
 clean:
-	rm -f $(addsuffix .pdf,$(TARGETS))
-	rm -f $(addsuffix .dot,$(TARGETS))
+	rm -f $(DOTS)
 

docs/source/code_examples/techmap/Makefile

@@ -1,8 +1,8 @@
 PROGRAM_PREFIX :=
 
-YOSYS ?= ../../../$(PROGRAM_PREFIX)yosys
+YOSYS ?= ../../../../$(PROGRAM_PREFIX)yosys
 
-all: red_or3x1.dot sym_mul.dot mymul.dot mulshift.dot addshift.dot
+dots: red_or3x1.dot sym_mul.dot mymul.dot mulshift.dot addshift.dot
 
 red_or3x1.dot: red_or3x1_*
 	$(YOSYS) red_or3x1_test.ys
@@ -18,4 +18,3 @@ mulshift.dot: mulshift_*
 
 addshift.dot: addshift_*
 	$(YOSYS) addshift_test.ys
-

docs/source/getting_started/scripting_intro.rst

@@ -128,31 +128,31 @@ different stages of the yosys tool flow.
 
 .. _xdot: https://github.com/jrfonseca/xdot.py
 
-.. code-block:: console
-   :caption: Yosys script with :cmd:ref:`show` commands and example design
-   :name: show_src
+.. literalinclude:: /code_examples/show/example.ys
+    :language: yoscrypt
+    :caption: docs/source/code_examples/show/example.ys
 
-   $ cat example.ys
-   read_verilog example.v
-   show -pause
-   proc
-   show -pause
-   opt
-   show -pause
+.. literalinclude:: /code_examples/show/example.v
+    :language: Verilog
+    :caption: docs/source/code_examples/show/example.v
 
-   $ cat example.v
-   module example(input clk, a, b, c,
-                  output reg [1:0] y);
-       always @(posedge clk)
-           if (c)
-               y <= c ? a + b : 2'd0;
-   endmodule
+.. role:: yoscrypt(code)
+   :language: yoscrypt
 
-.. figure:: /_images/011/example_out.*
+.. figure:: /_images/code_examples/show/example_00.*
    :class: width-helper
-   :name: show_out
    
-   Output of the three :cmd:ref:`show` commands from :numref:`show_src`
+   ``example_00`` - shown after :yoscrypt:`read_verilog example.v`
+
+.. figure:: /_images/code_examples/show/example_01.*
+   :class: width-helper
+   
+   ``example_01`` - shown after :yoscrypt:`proc`
+
+.. figure:: /_images/code_examples/show/example_02.*
+   :class: width-helper
+   
+   ``example_02`` - shown after :yoscrypt:`opt`
 
 A circuit diagram is generated for the design in its current state. Various
 options can be used to change the appearance of the circuit diagram, set the

docs/source/introduction.rst

@@ -37,7 +37,7 @@ domain of behavioural, rtl and logic synthesis. Yosys is designed to be
 extensible and therefore is a good basis for implementing custom synthesis tools
 for specialised tasks.
 
-.. figure:: /_images/levels_of_abstraction.*
+.. figure:: /_images/primer/levels_of_abstraction.*
     :class: width-helper
     :name: fig:Levels_of_abstraction
 

docs/source/using_yosys/more_scripting/interactive_investigation.rst

@@ -45,7 +45,7 @@ This script, when executed, will show the design after each of the three
 synthesis commands. We will now look at each of these diagrams and explain what
 is shown.
 
-.. figure:: /_images/011/example_00.*
+.. figure:: /_images/code_examples/show/example_00.*
    :class: width-helper
    
    Output of the first :cmd:ref:`show` command in :numref:`example_ys`
@@ -77,7 +77,7 @@ original ``always``-block in the second line. Note how the multiplexer from the
 The :cmd:ref:`proc` command transforms the process from the first diagram into a
 multiplexer and a d-type flip-flop, which brings us to the second diagram:
 
-.. figure:: /_images/011/example_01.*
+.. figure:: /_images/code_examples/show/example_01.*
    :class: width-helper
    
    Output of the second :cmd:ref:`show` command in :numref:`example_ys`
@@ -99,7 +99,7 @@ call :cmd:ref:`clean` before calling :cmd:ref:`show`.
 In this script we directly call :cmd:ref:`opt` as the next step, which finally
 leads us to the third diagram: 
 
-.. figure:: /_images/011/example_02.*
+.. figure:: /_images/code_examples/show/example_02.*
    :class: width-helper
    :name: example_out
    
@@ -126,7 +126,7 @@ native objects. While this provides great advantages when analyzing circuits
 that operate on wide integers, it also introduces some additional complexity
 when the individual bits of of a signal vector are accessed.
 
-.. figure:: /_images/011/splice.*
+.. figure:: /_images/code_examples/show/splice.*
    :class: width-helper
    :name: splice_dia
 
@@ -154,7 +154,7 @@ Gate level netlists
 :numref:`first_pitfall` shows two common pitfalls when working with designs
 mapped to a cell library: 
 
-.. figure:: /_images/011/cmos_00.*
+.. figure:: /_images/code_examples/show/cmos_00.*
    :class: width-helper
    :name: first_pitfall
 
@@ -167,7 +167,7 @@ all ports are drawn on the left side the cells are awkwardly arranged in a large
 column. Secondly the two-bit vector ``y`` requires breakout-boxes for its
 individual bits, resulting in an unnecessary complex diagram.
 
-.. figure:: /_images/011/cmos_01.*
+.. figure:: /_images/code_examples/show/cmos_01.*
    :class: width-helper
    :name: second_pitfall
 
@@ -350,10 +350,10 @@ reorganizing a module in Yosys and checking the resulting circuit.
    :caption: ``docs/source/code_examples/scrambler/scrambler.ys``
    :end-before: cd ..
 
-.. figure:: /_images/res/PRESENTATION_ExOth/scrambler_p01.*
+.. figure:: /_images/code_examples/scrambler/scrambler_p01.*
     :class: width-helper
 
-.. figure:: /_images/res/PRESENTATION_ExOth/scrambler_p02.*
+.. figure:: /_images/code_examples/scrambler/scrambler_p02.*
     :class: width-helper
 
 Analyzing the resulting circuit with :doc:`/cmd/eval`:
@@ -430,7 +430,7 @@ if the circuit under investigation is encapsulated in a separate module.
 
 Recall the ``memdemo`` design from :ref:`advanced_logic_cones`:
 
-.. figure:: /_images/011/memdemo_00.*
+.. figure:: /_images/code_examples/selections/memdemo_00.*
    :class: width-helper
    
    ``memdemo``
@@ -451,18 +451,18 @@ The ``-name`` option is used to specify the name of the new module and also the
 name of the new cell in the current module. The resulting circuits are shown
 below.
 
-.. figure:: /_images/011/submod_02.*
+.. figure:: /_images/code_examples/selections/submod_02.*
    :class: width-helper
    
    ``outstage``
 
-.. figure:: /_images/011/submod_03.*
+.. figure:: /_images/code_examples/selections/submod_03.*
    :class: width-helper
    :name: selstage
    
    ``selstage``
 
-.. figure:: /_images/011/submod_01.*
+.. figure:: /_images/code_examples/selections/submod_01.*
    :class: width-helper
    
    ``scramble``

docs/source/using_yosys/more_scripting/selections.rst

@@ -154,7 +154,7 @@ to mark portions of code for analysis.)
 Selecting ``a:sumstuff`` in this module will yield the following circuit
 diagram:
 
-.. figure:: /_images/011/sumprod_00.*
+.. figure:: /_images/code_examples/selections/sumprod_00.*
    :class: width-helper
    :name: sumprod_00
 
@@ -171,7 +171,7 @@ be achieved using the ``%x`` action, that broadens the selection, i.e. for each
 selected wire it selects all cells connected to the wire and vice versa. So
 :yoscrypt:`show a:sumstuff %x` yields the diagram shown in :numref:`sumprod_01`:
 
-.. figure:: /_images/011/sumprod_01.*
+.. figure:: /_images/code_examples/selections/sumprod_01.*
    :class: width-helper
    :name: sumprod_01
 
@@ -192,22 +192,22 @@ input ports.
 
 The following sequence of diagrams demonstrates this step-wise expansion:
 
-.. figure:: /_images/011/sumprod_02.*
+.. figure:: /_images/code_examples/selections/sumprod_02.*
    :class: width-helper
 
    Output of ``show prod`` on :numref:`sumprod`
 
-.. figure:: /_images/011/sumprod_03.*
+.. figure:: /_images/code_examples/selections/sumprod_03.*
    :class: width-helper
 
    Output of ``show prod %ci`` on :numref:`sumprod`
 
-.. figure:: /_images/011/sumprod_04.*
+.. figure:: /_images/code_examples/selections/sumprod_04.*
    :class: width-helper
 
    Output of ``show prod %ci %ci`` on :numref:`sumprod`
 
-.. figure:: /_images/011/sumprod_05.*
+.. figure:: /_images/code_examples/selections/sumprod_05.*
    :class: width-helper
 
    Output of ``show prod %ci %ci %ci`` on :numref:`sumprod`
@@ -242,7 +242,7 @@ We synthesize the circuit using ``proc; opt; memory; opt`` and change to the
 ``memdemo`` module with ``cd memdemo``. If we type :cmd:ref:`show` now we see
 the diagram shown in :numref:`memdemo_00`.
 
-.. figure:: /_images/011/memdemo_00.*
+.. figure:: /_images/code_examples/selections/memdemo_00.*
    :class: width-helper
    :name: memdemo_00
    
@@ -287,7 +287,7 @@ Or we could decide to tell the ``%ci`` action to not follow the ``CLK`` input:
 
    show y %ci2:-[CLK]
 
-.. figure:: /_images/011/memdemo_01.*
+.. figure:: /_images/code_examples/selections/memdemo_01.*
    :class: width-helper
    :name: memdemo_01
    
@@ -379,7 +379,7 @@ Example:
    :caption: ``docs/source/code_examples/selections/select.ys``
    :name: select_ys
 
-.. figure:: /_images/res/PRESENTATION_ExAdv/select.*
+.. figure:: /_images/code_examples/selections/select.*
     :class: width-helper
 
     Circuit diagram produced by :numref:`select_ys`

docs/source/yosys_internals/extensions.rst

@@ -58,7 +58,7 @@ provides.
 This document will focus on the much simpler version of RTLIL left after the
 commands :cmd:ref:`proc` and :cmd:ref:`memory` (or ``memory -nomap``):
 
-.. figure:: /_images/simplified_rtlil.*
+.. figure:: /_images/internals/simplified_rtlil.*
     :class: width-helper
     :name: fig:Simplified_RTLIL
 

docs/source/yosys_internals/flow/control_and_data.rst

@@ -9,7 +9,7 @@ a predetermined order, each consuming the data generated by the last subsystem
 and generating the data for the next subsystem (see :numref:`Fig. %s
 <fig:approach_flow>`).
 
-.. figure:: /_images/approach_flow.*
+.. figure:: /_images/internals/approach_flow.*
 	:class: width-helper
 	:name: fig:approach_flow
 

docs/source/yosys_internals/flow/overview.rst

@@ -40,7 +40,7 @@ possible it is key that (1) all passes operate on the same data structure
 (RTLIL) and (2) that this data structure is powerful enough to represent the
 design in different stages of the synthesis.
 
-.. figure:: /_images/overview_flow.*
+.. figure:: /_images/internals/overview_flow.*
 	:class: width-helper
 	:name: fig:Overview_flow
 

docs/source/yosys_internals/flow/verilog_frontend.rst

@@ -9,7 +9,7 @@ abstract syntax tree (AST) representation of the input. This AST representation
 is then passed to the AST frontend that converts it to RTLIL data, as
 illustrated in :numref:`Fig. %s <fig:Verilog_flow>`.
 
-.. figure:: /_images/verilog_flow.*
+.. figure:: /_images/internals/verilog_flow.*
 	:class: width-helper
 	:name: fig:Verilog_flow
 

docs/source/yosys_internals/formats/rtlil_rep.rst

@@ -23,7 +23,7 @@ pass is reading an auxiliary Verilog file such as a cell library, it might
 create an additional ``RTLIL::Design`` object and call the Verilog frontend with
 this other object to parse the cell library.
 
-.. figure:: /_images/overview_rtlil.*
+.. figure:: /_images/internals/overview_rtlil.*
 	:class: width-helper
 	:name: fig:Overview_RTLIL