yosys/docs/source/code_examples/macc/macc_xilinx_test.ys

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read_verilog macc_xilinx_test.v
read_verilog -lib -icells macc_xilinx_unwrap_map.v
read_verilog -lib -icells macc_xilinx_xmap.v
hierarchy -check ;;
show -prefix macc_xilinx_test1a -format dot -notitle test1
show -prefix macc_xilinx_test2a -format dot -notitle test2
techmap -map macc_xilinx_swap_map.v;;
show -prefix macc_xilinx_test1b -format dot -notitle test1
show -prefix macc_xilinx_test2b -format dot -notitle test2
techmap -map macc_xilinx_wrap_map.v
connwrappers -unsigned $__mul_wrapper Y Y_WIDTH \
-unsigned $__add_wrapper Y Y_WIDTH;;
show -prefix macc_xilinx_test1c -format dot -notitle test1
show -prefix macc_xilinx_test2c -format dot -notitle test2
design -push
read_verilog macc_xilinx_xmap.v
techmap -map macc_xilinx_swap_map.v
techmap -map macc_xilinx_wrap_map.v;;
design -save __macc_xilinx_xmap
design -pop
extract -constports -ignore_parameters \
-map %__macc_xilinx_xmap \
-swap $__add_wrapper A,B ;;
show -prefix macc_xilinx_test1d -format dot -notitle test1
show -prefix macc_xilinx_test2d -format dot -notitle test2
techmap -map macc_xilinx_unwrap_map.v;;
show -prefix macc_xilinx_test1e -format dot -notitle test1
show -prefix macc_xilinx_test2e -format dot -notitle test2
design -load __macc_xilinx_xmap
show -prefix macc_xilinx_xmap -format dot -notitle