mirror of https://github.com/YosysHQ/yosys.git
742ec78ca3
Fifo code based on SBY quick start. Instead of showing the full design we are (currently) focusing on a single output (rdata), using `%ci*` to get the subcircuit it relies on. |
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| .. | ||
| _downloads | ||
| _images | ||
| _static | ||
| _templates | ||
| appendix | ||
| code_examples | ||
| getting_started | ||
| using_yosys | ||
| yosys_internals | ||
| appendix.rst | ||
| bib.rst | ||
| cmd_ref.rst | ||
| conf.py | ||
| index.rst | ||
| introduction.rst | ||
| literature.bib | ||
| requirements.txt | ||
| test_suites.rst | ||