mirror of https://github.com/YosysHQ/yosys.git
742ec78ca3
Fifo code based on SBY quick start. Instead of showing the full design we are (currently) focusing on a single output (rdata), using `%ci*` to get the subcircuit it relies on. |
||
|---|---|---|
| .. | ||
| example_synth.rst | ||
| index.rst | ||
| installation.rst | ||
| scripting_intro.rst | ||