Eddie Hung 7a62ee57b4 Merge pull request #2024 from YosysHQ/eddie/primitive_src ... verilog: set src attribute for primitives		2020-05-05 06:49:18 -07:00
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aiger	tests: aiger test for wire->start_offset != 0	2020-05-02 10:00:32 -07:00
arch	intel_alm: work around a Quartus ICE	2020-04-23 11:03:28 +02:00
asicworld	…
bram	…
errors	…
fsm	…
hana	…
liberty	…
lut	…
memfile	Added 'set -e' into tests/memfile/run-test.sh	2020-02-06 10:45:40 -03:00
memories	…
opt	Add testcase for #2010	2020-05-01 14:07:33 -07:00
opt_share	…
proc	proc_clean: fix order of switch insertion.	2019-08-19 16:44:23 +00:00
realmath	…
rpc	rpc test: make frontend listen before launching yosys & introduce safeguard if yosys errors	2020-03-06 15:29:01 +01:00
sat	Merge pull request #1638 from YosysHQ/eddie/fix1631	2020-02-05 19:31:18 +01:00
select	Merge pull request #1949 from YosysHQ/eddie/select_blackbox	2020-04-22 15:35:05 -07:00
share	…
simple	Add dynamic slicing Verilog testcase	2020-03-31 11:51:31 -07:00
simple_abc9	Update simple_abc9 tests	2020-02-27 10:17:29 -08:00
smv	…
sva	…
svinterfaces	…
svtypes	support using previously declared types/localparams/params in package	2020-04-07 00:38:15 -04:00
techmap	tests: zinit for new types	2020-04-14 13:08:37 -07:00
tools	…
unit	…
various	Merge pull request #2024 from YosysHQ/eddie/primitive_src	2020-05-05 06:49:18 -07:00
vloghtb	…