Eddie Hung 8fa74287a7 As per @daveshah1 remove async DFF timing from xilinx		2019-06-14 12:43:20 -07:00
..
tests	Improved xilinx "bram1" test	2015-04-09 17:12:12 +02:00
.gitignore	Added support for initialized xilinx brams	2015-04-06 17:07:10 +02:00
Makefile.inc	Rename +/xilinx/abc.{box,lut} -> abc_xc7.{box,lut}	2019-06-14 10:51:11 -07:00
abc_xc7.box	As per @daveshah1 remove async DFF timing from xilinx	2019-06-14 12:43:20 -07:00
abc_xc7.lut	Update delays based on SymbiFlow/prjxray-db	2019-06-14 11:33:10 -07:00
arith_map.v	Instead of MUXCY/XORCY use CARRY4 (with timing)	2019-05-21 16:19:45 -07:00
brams.txt	Added read-enable to memory model	2015-09-25 12:23:11 +02:00
brams_bb.v	Remove WIP ABC9 flop support	2019-06-14 10:37:52 -07:00
brams_init.py	Squelch trailing whitespace, including meta-whitespace	2018-03-11 16:03:41 +01:00
brams_map.v	Revert BRAM WRITE_MODE changes.	2019-03-04 09:22:22 -08:00
cells_map.v	Fix name clash	2019-06-13 14:27:07 -07:00
cells_sim.v	Remove WIP ABC9 flop support	2019-06-14 10:37:52 -07:00
cells_xtra.sh	Typo	2019-05-28 09:36:01 -07:00
cells_xtra.v	Add whitebox support to DRAM	2019-05-23 08:58:57 -07:00
drams.txt	Add "min bits" and "min wports" to xilinx dram rules	2019-05-23 11:32:28 -07:00
drams_map.v	Xilinx DRAMS: RAM64X1D, RAM128X1D	2015-04-09 13:37:07 +02:00
ff_map.v	Cleanup	2019-06-05 12:28:46 -07:00
lut_map.v	Changes required for VPR place and route synth_xilinx.	2019-03-01 12:02:27 -08:00
synth_xilinx.cc	Add XC7_WIRE_DELAY macro to synth_xilinx.cc	2019-06-14 11:38:22 -07:00