mirror of https://github.com/YosysHQ/yosys.git
95 lines
3.1 KiB
Verilog
95 lines
3.1 KiB
Verilog
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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// ============================================================================
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// LUT mapping
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`ifndef _NO_LUTS
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module \$lut (A, Y);
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parameter WIDTH = 0;
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parameter LUT = 0;
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input [WIDTH-1:0] A;
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output Y;
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generate
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if (WIDTH == 1) begin
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LUT1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
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.I0(A[0]));
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end else
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if (WIDTH == 2) begin
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LUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
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.I0(A[0]), .I1(A[1]));
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end else
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if (WIDTH == 3) begin
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LUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
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.I0(A[0]), .I1(A[1]), .I2(A[2]));
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end else
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if (WIDTH == 4) begin
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LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
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.I0(A[0]), .I1(A[1]), .I2(A[2]),
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.I3(A[3]));
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end else
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if (WIDTH == 5) begin
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LUT5 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
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.I0(A[0]), .I1(A[1]), .I2(A[2]),
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.I3(A[3]), .I4(A[4]));
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end else
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if (WIDTH == 6) begin
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LUT6 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
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.I0(A[0]), .I1(A[1]), .I2(A[2]),
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.I3(A[3]), .I4(A[4]), .I5(A[5]));
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end else
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if (WIDTH == 7) begin
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wire T0, T1;
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LUT6 #(.INIT(LUT[63:0])) fpga_lut_0 (.O(T0),
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.I0(A[0]), .I1(A[1]), .I2(A[2]),
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.I3(A[3]), .I4(A[4]), .I5(A[5]));
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LUT6 #(.INIT(LUT[127:64])) fpga_lut_1 (.O(T1),
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.I0(A[0]), .I1(A[1]), .I2(A[2]),
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.I3(A[3]), .I4(A[4]), .I5(A[5]));
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MUXF7 fpga_mux_0 (.O(Y), .I0(T0), .I1(T1), .S(A[6]));
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end else
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if (WIDTH == 8) begin
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wire T0, T1, T2, T3, T4, T5;
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LUT6 #(.INIT(LUT[63:0])) fpga_lut_0 (.O(T0),
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.I0(A[0]), .I1(A[1]), .I2(A[2]),
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.I3(A[3]), .I4(A[4]), .I5(A[5]));
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LUT6 #(.INIT(LUT[127:64])) fpga_lut_1 (.O(T1),
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.I0(A[0]), .I1(A[1]), .I2(A[2]),
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.I3(A[3]), .I4(A[4]), .I5(A[5]));
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LUT6 #(.INIT(LUT[191:128])) fpga_lut_2 (.O(T2),
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.I0(A[0]), .I1(A[1]), .I2(A[2]),
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.I3(A[3]), .I4(A[4]), .I5(A[5]));
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LUT6 #(.INIT(LUT[255:192])) fpga_lut_3 (.O(T3),
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.I0(A[0]), .I1(A[1]), .I2(A[2]),
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.I3(A[3]), .I4(A[4]), .I5(A[5]));
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MUXF7 fpga_mux_0 (.O(T4), .I0(T0), .I1(T1), .S(A[6]));
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MUXF7 fpga_mux_1 (.O(T5), .I0(T2), .I1(T3), .S(A[6]));
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MUXF8 fpga_mux_2 (.O(Y), .I0(T4), .I1(T5), .S(A[7]));
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end else begin
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wire _TECHMAP_FAIL_ = 1;
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end
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endgenerate
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endmodule
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`endif
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