yosys/techlibs/greenpak4
Larry Doolittle 7a40294e93 techlibs/greenpak4/cells_map.v: Harmonize whitespace within lut module 2019-02-26 09:40:46 -08:00
..
Makefile.inc Added blackbox $__COUNT_ cell model 2017-09-01 06:44:28 -07:00
cells_blackbox.v Added RESET_TO_MAX parameter to $__COUNT_ cell. Cannot yet be extracted. 2017-09-14 10:26:32 -07:00
cells_latch.v greenpak4: Can now techmap inferred D latches (without set/reset or output inverter) 2016-12-10 18:46:36 +08:00
cells_map.v techlibs/greenpak4/cells_map.v: Harmonize whitespace within lut module 2019-02-26 09:40:46 -08:00
cells_sim.v Refactoring: moved modules still in cells_sim to cells_sim_wip 2017-09-01 06:44:15 -07:00
cells_sim_ams.v Moved GP_POR out of digital cells b/c it has delays 2017-08-14 10:45:39 -07:00
cells_sim_digital.v Fixed typo in error message 2017-09-01 06:45:10 -07:00
cells_sim_wip.v Refactoring: moved modules still in cells_sim to cells_sim_wip 2017-09-01 06:44:15 -07:00
gp_dff.lib Fixed indenting in techlibs/greenpak4/gp_dff.lib 2016-03-29 13:44:14 +02:00
greenpak4_dffinv.cc Consistent use of 'override' for virtual methods in derived classes. 2018-07-20 23:51:06 -07:00
synth_greenpak4.cc Fix typographical and grammatical errors and inconsistencies. 2019-01-02 13:12:17 +00:00