yosys/frontends/verilog
Jim Paris 4a229e5b95 Support SystemVerilog `` extension for macros 2018-05-17 00:09:56 -04:00
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.gitignore Updated .gitignore file for ilang and verilog frontends 2014-10-15 01:14:38 +02:00
Makefile.inc Adjust makefiles to work with out-of-tree builds 2015-08-12 15:04:44 +02:00
const2ast.cc Fixed segfault on invalid verilog constant 1'b_ 2015-09-22 08:13:09 +02:00
preproc.cc Support SystemVerilog `` extension for macros 2018-05-17 00:09:56 -04:00
verilog_frontend.cc Replace -ignore_redef with -[no]overwrite 2018-05-03 15:25:59 +02:00
verilog_frontend.h Remember global declarations and defines accross read_verilog calls 2016-11-15 12:42:43 +01:00
verilog_lexer.l Support more character literals 2018-05-03 12:35:01 +02:00
verilog_parser.y Add statement labels for immediate assertions 2018-04-13 11:52:28 +02:00