Andrew Zonenberg 3a404be62a Updated PGEN model to have level triggered reset (matches actual hardware behavior		2017-08-15 09:18:27 -07:00
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altera_intel	Squelch trailing whitespace	2017-04-12 15:11:09 +02:00
common	Add dff2ff.v techmap file	2017-05-31 11:45:58 +02:00
coolrunner2	coolrunner2: Add INVERT parameter to some BUFGs	2017-08-14 12:13:33 -07:00
gowin	Indenting fixes in gowin sim cell lib	2016-11-08 18:54:00 +01:00
greenpak4	Updated PGEN model to have level triggered reset (matches actual hardware behavior	2017-08-15 09:18:27 -07:00
ice40	iCE40 flow is not experimental anymore	2016-11-01 11:32:02 +01:00
xilinx	Add techlibs/xilinx/lut2lut.v	2017-07-10 12:09:05 +02:00
.gitignore	added .gitignore files	2013-01-05 11:19:11 +01:00