Martin Povišer dc746080f5 Merge pull request #4298 from povik/kogge-stone ... techmap: Add a Kogge-Stone option for `$lcu` mapping		2024-04-08 16:46:06 +02:00
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choices	techmap: Note down iteration in Kogge-Stone	2024-04-08 16:45:40 +02:00
.gitignore	…
Makefile.inc	techmap: Split out Kogge-Stone into a separate file	2024-03-27 11:07:24 +01:00
abc9_map.v	techmap: Add support for [] wildcards in techmap_celltype.	2020-08-02 22:46:48 +02:00
abc9_model.v	abc9: fix SCC issues (#2694)	2021-03-29 22:01:57 -07:00
abc9_unmap.v	abc9: fix SCC issues (#2694)	2021-03-29 22:01:57 -07:00
adff2dff.v	Fix syntax error in adff2dff.v	2021-02-24 01:07:34 +01:00
cellhelp.py	Progress on cell help messages	2015-10-17 02:35:19 +02:00
cells.lib	…
cmp2lcu.v	verilog: significant block scoping improvements	2021-01-31 09:42:09 -05:00
cmp2lut.v	verilog: significant block scoping improvements	2021-01-31 09:42:09 -05:00
cmp2softlogic.v	techlibs: Add `cmp2softlogic.v` to common	2023-11-13 10:42:12 +01:00
dff2ff.v	Add force_downto and force_upto wire attributes.	2020-05-19 01:42:40 +02:00
gate2lut.v	Fix invalid verilog syntax	2020-03-14 14:33:44 +01:00
gen_fine_ffs.py	Add $aldff and $aldffe: flip-flops with async load.	2021-10-02 18:12:52 +02:00
mul2dsp.v	Fix files with CRLF line endings	2021-06-09 12:16:33 +02:00
pmux2mux.v	…
prep.cc	Run `future` as part of `prep`	2023-09-13 11:32:36 +02:00
simcells.v	Add $aldff and $aldffe: flip-flops with async load.	2021-10-02 18:12:52 +02:00
simlib.v	fixup	2024-04-04 18:16:58 +02:00
smtmap.v	Add smtmap.v describing the smt2 backend's behavior for undef bits	2022-10-20 15:48:18 +02:00
synth.cc	synth: Fix out-of-sync help message	2024-03-06 14:55:43 +01:00
techmap.v	techmap: Split out Kogge-Stone into a separate file	2024-03-27 11:07:24 +01:00