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fixup

This commit is contained in:
Emil J. Tywoniak 2024-04-04 18:16:58 +02:00
parent a580a7c82c
commit 9510293a94
2 changed files with 14 additions and 6 deletions
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11
docs/source/yosys_internals/formats/cell_library.rst
View File

@ -632,8 +632,9 @@ If the second signal in such a pair is zero length, no multiplication is necessa
In this pseudocode, ``u(foo)`` means an unsigned int that's foo bits long.
The CONFIG parameter carries the following information:
.. code-block::
:force:
struct CONFIG {
u4 num_bits;
struct port_field {
@ -645,8 +646,9 @@ The CONFIG parameter carries the following information:
};
The A cell port carries the following information:
.. code-block::
:force:
struct A {
u(CONFIG.port_field[0].factor1_len) port0factor1;
u(CONFIG.port_field[0].factor2_len) port0factor2;
@ -660,10 +662,11 @@ A factor2 having a zero length implies factor2 is replaced with a constant 1.
Additionally, B is an array of 1-bit-wide unsigned integers to also be summed up.
Finally, we have:
.. code-block::
:force:
Y = port0factor1 * port0factor2 + port1factor1 * port1factor2 + ...
* B[0] + B[1] + ...
+ B[0] + B[1] + ...
Specify rules
~~~~~~~~~~~~~

9
techlibs/common/simlib.v
View File

@ -907,8 +907,13 @@ endmodule
//- $macc (A, B, Y)
//-
//- Multiply and accumulate.
//- A building block for summing any number of negated and unnegated signals and arithmetic products of pairs of signals. Cell port A concatenates pairs of signals to be multiplied together. When the second signal in a pair is zero length, a constant 1 is used instead as the second factor. Cell port B concatenates 1-bit-wide signals to also be summed, such as "carry in" in adders.
//- Typically created by the `alumacc` pass, which transforms $add and $mul into $macc cells.
//- A building block for summing any number of negated and unnegated signals
//- and arithmetic products of pairs of signals. Cell port A concatenates pairs
//- of signals to be multiplied together. When the second signal in a pair is zero
//- length, a constant 1 is used instead as the second factor. Cell port B
//- concatenates 1-bit-wide signals to also be summed, such as "carry in" in adders.
//- Typically created by the `alumacc` pass, which transforms $add and $mul
//- into $macc cells.
module \$macc (A, B, Y);
parameter A_WIDTH = 0;