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APPNOTE_011_Design_Investigation
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Improved "make manual" and "make clean"
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2014-02-11 12:55:58 +01:00 |
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CHAPTER_Eval
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Renamed manual/FILES_* directories
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2014-01-28 06:55:47 +01:00 |
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CHAPTER_Prog
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Refactoring: Renamed RTLIL::Design::modules to modules_
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2014-07-27 11:18:30 +02:00 |
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CHAPTER_StateOfTheArt
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Renamed manual/FILES_* directories
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2014-01-28 06:55:47 +01:00 |
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PRESENTATION_ExAdv
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Progress in presentation
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2014-02-21 14:59:59 +01:00 |
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PRESENTATION_ExOth
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Progress in presentation
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2014-06-21 16:33:33 +02:00 |
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PRESENTATION_ExSyn
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Progress in presentation
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2014-06-21 16:33:33 +02:00 |
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PRESENTATION_Intro
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Progress in presentation
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2014-06-26 22:05:39 +02:00 |
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PRESENTATION_Prog
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Added module->design and cell->module, wire->module pointers
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2014-07-31 14:11:39 +02:00 |
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.gitignore
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presentation progress
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2014-01-29 12:15:38 +01:00 |
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APPNOTE_010_Verilog_to_BLIF.tex
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Fixed bug in example prog in appnote 011
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2013-12-05 18:15:14 +01:00 |
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APPNOTE_011_Design_Investigation.tex
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Finished AppNote 011
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2013-12-08 15:12:32 +01:00 |
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CHAPTER_Appnotes.tex
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Added Yosys Manual
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2013-07-20 15:19:12 +02:00 |
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CHAPTER_Approach.tex
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Typos and grammar fixes through chapter 4.
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2014-05-02 03:08:40 -06:00 |
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CHAPTER_Auxlibs.tex
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Replaced sha1 implementation
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2014-08-01 19:01:10 +02:00 |
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CHAPTER_Auxprogs.tex
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Added Yosys Manual
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2013-07-20 15:19:12 +02:00 |
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CHAPTER_Basics.tex
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Typos and grammar fixes through chapter 2.
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2014-04-11 02:42:59 -06:00 |
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CHAPTER_CellLib.tex
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Changed the $mem/$memwr WR_EN input to a per-data-bit enable signal
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2014-07-16 11:38:02 +02:00 |
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CHAPTER_Eval.tex
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Added Yosys Manual
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2013-07-20 15:19:12 +02:00 |
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CHAPTER_Intro.tex
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Typos and grammar fixes through chapter 2.
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2014-04-11 02:42:59 -06:00 |
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CHAPTER_Optimize.tex
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Added Yosys Manual
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2013-07-20 15:19:12 +02:00 |
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CHAPTER_Overview.tex
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Typos and grammar fixes through chapter 4.
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2014-05-02 03:08:40 -06:00 |
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CHAPTER_Prog.tex
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Renamed manual/FILES_* directories
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2014-01-28 06:55:47 +01:00 |
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CHAPTER_StateOfTheArt.tex
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Renamed manual/FILES_* directories
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2014-01-28 06:55:47 +01:00 |
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CHAPTER_Techmap.tex
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Renamed "stdcells.v" to "techmap.v"
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2014-07-31 02:32:00 +02:00 |
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CHAPTER_Verilog.tex
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Added RTLIL and Liberty syntax highlighting to manual
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2013-07-25 14:00:16 +02:00 |
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PRESENTATION_ExAdv.tex
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Progress in presentation
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2014-06-26 22:05:39 +02:00 |
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PRESENTATION_ExOth.tex
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Progress in presentation
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2014-06-26 22:05:39 +02:00 |
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PRESENTATION_ExSyn.tex
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Progress in presentation
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2014-06-26 22:05:39 +02:00 |
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PRESENTATION_Intro.tex
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Progress in presentation
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2014-06-29 09:14:49 +02:00 |
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PRESENTATION_Prog.tex
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Progress in presentation
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2014-06-26 22:05:39 +02:00 |
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appnotes.sh
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Improved "make manual" and "make clean"
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2014-02-11 12:55:58 +01:00 |
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clean.sh
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POSIX find requires a path argument.
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2014-04-04 16:51:27 -06:00 |
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command-reference-manual.tex
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Updated manual/command-reference-manual.tex
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2013-12-28 12:14:47 +01:00 |
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literature.bib
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Added Yosys Manual
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2013-07-20 15:19:12 +02:00 |
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manual.sh
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Added first presentation slides
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2014-01-27 17:08:19 +01:00 |
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manual.tex
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Typos and grammar fixes through chapter 2.
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2014-04-11 02:42:59 -06:00 |
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presentation.sh
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Progress in presentation
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2014-06-22 12:50:29 +02:00 |
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presentation.tex
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small changes in presentation
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2014-07-02 06:16:31 +02:00 |
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weblinks.bib
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Replaced sha1 implementation
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2014-08-01 19:01:10 +02:00 |
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