Clifford Wolf 1de12e1efc Improved handling of initialized registers		2013-11-23 16:26:59 +01:00
..
.gitignore	added .gitignore files	2013-01-05 11:19:11 +01:00
Makefile.inc	initial import	2013-01-05 11:13:26 +01:00
const2ast.cc	Major redesign of expr width/sign detecion (verilog/ast frontend)	2013-07-09 14:31:57 +02:00
lexer.l	Enable {* .. *} feature per default (removes dependency to REJECT feature in flex)	2013-11-22 12:46:02 +01:00
parser.y	Improved handling of initialized registers	2013-11-23 16:26:59 +01:00
preproc.cc	Fixed O(n^2) performance bug in verilog preprocessor	2013-11-22 14:08:43 +01:00
verilog_frontend.cc	Renamed "placeholder" to "blackbox"	2013-11-22 15:01:12 +01:00
verilog_frontend.h	Enable {* .. *} feature per default (removes dependency to REJECT feature in flex)	2013-11-22 12:46:02 +01:00