mirror of https://github.com/YosysHQ/yosys.git
17163cf43a
The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $modfloor cell provides this flooring modulo (also known as "remainder" in several languages, but this name is ambiguous). This commit also fixes the handling of $mod in opt_expr, which was previously optimized as if it was $modfloor. |
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| .. | ||
| .gitignore | ||
| Makefile.inc | ||
| abc9_map.v | ||
| abc9_model.v | ||
| abc9_unmap.v | ||
| adff2dff.v | ||
| cellhelp.py | ||
| cells.lib | ||
| cmp2lcu.v | ||
| cmp2lut.v | ||
| dff2ff.v | ||
| gate2lut.v | ||
| gen_fine_ffs.py | ||
| mul2dsp.v | ||
| pmux2mux.v | ||
| prep.cc | ||
| simcells.v | ||
| simlib.v | ||
| synth.cc | ||
| techmap.v | ||