mirror of https://github.com/YosysHQ/yosys.git
17163cf43a
The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $modfloor cell provides this flooring modulo (also known as "remainder" in several languages, but this name is ambiguous). This commit also fixes the handling of $mod in opt_expr, which was previously optimized as if it was $modfloor. |
||
|---|---|---|
| .. | ||
| achronix | ||
| anlogic | ||
| common | ||
| coolrunner2 | ||
| easic | ||
| ecp5 | ||
| efinix | ||
| gowin | ||
| greenpak4 | ||
| ice40 | ||
| intel | ||
| intel_alm | ||
| sf2 | ||
| xilinx | ||
| .gitignore | ||