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tests
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xilinx: Add simulation model for DSP48 (Virtex 4).
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2020-01-29 01:40:00 +01:00 |
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.gitignore
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Added support for initialized xilinx brams
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2015-04-06 17:07:10 +02:00 |
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Makefile.inc
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xilinx: Use dfflegalize.
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2020-07-09 18:54:23 +02:00 |
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abc9_model.v
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abc9_ops: add -prep_bypass for auto bypass boxes; refactor
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2020-05-14 10:33:56 -07:00 |
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arith_map.v
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verilog: significant block scoping improvements
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2021-01-31 09:42:09 -05:00 |
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brams_init.py
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synth_xilinx: Initial Spartan 6 block RAM inference support.
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2019-07-11 14:45:48 +02:00 |
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cells_map.v
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xilinx: Use dfflegalize.
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2020-07-09 18:54:23 +02:00 |
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cells_sim.v
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xilinx: Add FDRSE_1, FDCPE_1.
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2021-01-27 00:32:00 +01:00 |
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cells_xtra.py
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xilinx: Add some missing blackbox cells.
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2020-12-21 05:34:26 +01:00 |
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cells_xtra.v
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xilinx: Add some missing blackbox cells.
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2020-12-21 05:34:26 +01:00 |
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ff_map.v
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xilinx: Use dfflegalize.
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2020-07-09 18:54:23 +02:00 |
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lut4_lutrams.txt
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xilinx: Add support for LUT RAM on LUT4-based devices.
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2020-02-07 09:03:22 +01:00 |
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lut6_lutrams.txt
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xilinx: Add support for LUT RAM on LUT4-based devices.
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2020-02-07 09:03:22 +01:00 |
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lut_map.v
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Add force_downto and force_upto wire attributes.
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2020-05-19 01:42:40 +02:00 |
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lutrams_map.v
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Merge branch 'eddie/xilinx_lutram' of github.com:YosysHQ/yosys into eddie/xilinx_lutram
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2019-12-16 12:06:47 -08:00 |
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mux_map.v
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Add force_downto and force_upto wire attributes.
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2020-05-19 01:42:40 +02:00 |
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synth_xilinx.cc
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Blackbox all whiteboxes after synthesis
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2021-03-17 21:07:20 +00:00 |
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xc2v_brams.txt
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xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
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2020-02-07 01:00:29 +01:00 |
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xc2v_brams_map.v
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xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
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2020-02-07 01:00:29 +01:00 |
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xc3s_mult_map.v
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xilinx: Support multiplier mapping for all families.
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2019-10-22 18:06:57 +02:00 |
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xc3sa_brams.txt
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xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
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2020-02-07 01:00:29 +01:00 |
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xc3sda_brams.txt
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xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
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2020-02-07 01:00:29 +01:00 |
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xc3sda_dsp_map.v
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xilinx_dsp: Initial DSP48A/DSP48A1 support.
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2019-12-22 20:51:14 +01:00 |
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xc4v_dsp_map.v
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xilinx: Support multiplier mapping for all families.
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2019-10-22 18:06:57 +02:00 |
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xc5v_dsp_map.v
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xilinx: Support multiplier mapping for all families.
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2019-10-22 18:06:57 +02:00 |
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xc6s_brams.txt
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xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
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2020-02-07 01:00:29 +01:00 |
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xc6s_brams_map.v
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xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
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2020-02-07 01:00:29 +01:00 |
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xc6s_dsp_map.v
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xilinx_dsp: Initial DSP48A/DSP48A1 support.
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2019-12-22 20:51:14 +01:00 |
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xc7_brams_map.v
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xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
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2020-02-07 01:00:29 +01:00 |
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xc7_dsp_map.v
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xilinx: do not make DSP48E1 a whitebox for ABC9 by default (#2325)
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2020-09-23 09:15:24 -07:00 |
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xc7_xcu_brams.txt
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xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
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2020-02-07 01:00:29 +01:00 |
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xcu_brams_map.v
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xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
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2020-02-07 01:00:29 +01:00 |
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xcu_dsp_map.v
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xilinx: Support multiplier mapping for all families.
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2019-10-22 18:06:57 +02:00 |
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xcup_urams.txt
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xilinx: Add URAM288 mapping for xcup
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2019-10-23 11:47:44 +01:00 |
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xcup_urams_map.v
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xilinx: Add URAM288 mapping for xcup
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2019-10-23 11:47:44 +01:00 |
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xilinx_dffopt.cc
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xilinx_dffopt: Don't crash on missing IS_*_INVERTED.
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2021-01-27 00:32:00 +01:00 |
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