Clifford Wolf 5ea2c53604 Add read_verilog anyseq/anyconst/allseq/allconst attribute support ... Signed-off-by: Clifford Wolf <clifford@clifford.at>		2018-04-06 14:35:11 +02:00
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.gitignore	Updated .gitignore file for ilang and verilog frontends	2014-10-15 01:14:38 +02:00
Makefile.inc	Adjust makefiles to work with out-of-tree builds	2015-08-12 15:04:44 +02:00
const2ast.cc	Fixed segfault on invalid verilog constant 1'b_	2015-09-22 08:13:09 +02:00
preproc.cc	Add support for "yosys -E"	2018-01-07 16:36:13 +01:00
verilog_frontend.cc	Bugfix in verilog_defaults argument parser	2017-12-24 17:21:37 +01:00
verilog_frontend.h	Remember global declarations and defines accross read_verilog calls	2016-11-15 12:42:43 +01:00
verilog_lexer.l	First draft of Verilog parser support for specify blocks and parameters.	2018-03-27 14:34:00 +02:00
verilog_parser.y	Add read_verilog anyseq/anyconst/allseq/allconst attribute support	2018-04-06 14:35:11 +02:00