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2379 Commits

Author SHA1 Message Date
Emil J 1113b88cb2
Merge pull request #4649 from YosysHQ/emil/synth-xilinx-json 
synth_xilinx: add -json
 2024-10-14 06:45:14 -07:00
Emil J. Tywoniak 785bd44da7 rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
Emil J. Tywoniak 981b267d97 synth_xilinx: add -json 2024-10-09 19:24:32 +02:00
Martin Povišer 9018d06a33 quicklogic: Avoid carry chains in division mapping 
The default mapping rules for division-like operations (div/divfloor/
mod/modfloor) invoke subtractions which can get mapped to carry chains
in FPGA flows. Optimizations across carry chains are weak, so in
practice this ends up too costly compared to implementing the division
purely in soft logic.

For this reason arrange for `techmap.v` ignoring division operations
under `-D NODIV`, and use this mode in `synth_quicklogic` to avoid carry
chains for divisions.
 2024-09-19 12:18:47 +02:00
Martin Povišer eeffca9470 simlib: Add `$buf` disclaimer 2024-09-17 10:46:20 +02:00
Claire Xenia Wolf 4d469f461b Add coarse-grain $buf buffer cell type 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2024-09-17 10:46:20 +02:00
YRabbit ab35dff702 Gowin. Add the EMCU primitive. 
EMCU is a micro-processor based on ARM Cortex-M3 embedded in the
GW1NSR-4C chip used in the Tangnano4k board.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2024-09-11 10:18:51 +10:00
Miodrag Milanović 598d010349
Merge pull request #4504 from YosysHQ/nanoxplore 
NanoXplore synthesis
 2024-09-03 10:19:44 +02:00
Miodrag Milanovic 556c705a89 Cleanup of synth_nanoxplore pass 2024-09-03 10:15:50 +02:00
Emil J d901b28d2c
Merge pull request #4546 from NachtSpyder04/main 
[Docs]:Add new cell type help messages
 2024-08-19 15:50:41 +02:00
David Lanzendörfer d1b767ea8b Adding missing to Gowin tech files 
Without OSER4_MEM, IDES4_MEM and DQS the synthesis of my Rocket Chip
design for my Sipeed Tang FPGA fails.
 2024-08-18 19:38:31 +01:00
NachtSpyder04 aa60255e0e update help messages that went beyond line length limit 2024-08-18 20:27:35 +05:30
Saish Karole 34aabd56cc
Apply suggestions from code review 
Co-authored-by: Martin Povišer <povik@cutebit.org>
 2024-08-18 20:12:53 +05:30
Saish Karole d80d4dc51c
[Docs]:Add new cell type help messages (#1) 
* add shift operators description

* update shift operations' descriptions, add desciptions for add, sub, logic_*, tribuf, mux, demux, concat, pow and comparison operators
 2024-08-17 15:47:00 +05:30
Miodrag Milanovic 54d237ff82 add min_ce_use and min_srst_use parameters 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 14e43139cb Run opt_merge, helps with inverted reset/load signals 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 220ddeac4d Set -mince and -minsrst 2024-08-15 17:50:36 +02:00
Miodrag Milanovic dbf1d037e8 Cleanup 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 7bf623a0c7 Fix simulation model warnings 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 262ad03cd3 Add iopads by default add option to disable and keep old one for compatibility 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 8f806c0d12 Added DDFR support 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 1a6e5c671f Add meminit handling for NX_RFB_U 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 6876a27547 Add NX_DFR simulation model 2024-08-15 17:50:36 +02:00
Miodrag Milanovic eb30be6189 Impulse does not support these types but NG-ULTRA architecture does 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 7601dc740b Some memory types are only supported on NG-LARGE 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 4372487a6f raw must be 16 bits for nx tools to work 2024-08-15 17:50:36 +02:00
Miodrag Milanovic f8ae93c0ea run setundef for all x inputs 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 40f05009e3 Fix CY chaining and CI injection 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 596506b88b Add NX_XCDC_U to wrappers 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 8909a42796 Better wire check 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 5766555642 Support brams with initialization 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 4aaab8f395 start adding wfg model 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 41a86fdb2c fix 2024-08-15 17:50:36 +02:00
Miodrag Milanovic f4d8ea4c40 Start adding RFB simulation models 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 8eb099c1f4 remove debug attribute 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 829dd62054 block ram mapping for standard modes 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 9d6b47466f Add RF initialization 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 7e4aef06e4 Add register file mapping 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 11449ec493 Cleanup not connected ports 2024-08-15 17:50:36 +02:00
Miodrag Milanovic f9f68c3cd1 Split sim models into multiple files and implement few 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 04d3672121 No need for LOC 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 41ae513d60 support other I/O configurations 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 645888cff5 cleanup 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 9a9190b67d enable dff context initialization 2024-08-15 17:50:36 +02:00
Miodrag Milanovic dc16bdd85b DFF reset and context must be in sync 2024-08-15 17:50:36 +02:00
Miodrag Milanovic cb45f8b69d Fixed of mapping and initialization 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 198fc963ca Add new DFF types, and added "-nodffe" option 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 0c4bbf7e4b Fix existing DFF mapping and add new types 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 94675a5e0b Fix dff simulation model 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 606439b44c do not leave NX_RAM empty to prevent removing it 2024-08-15 17:50:36 +02:00