Claire Wolf
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fa8cb3e35d
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Revert "Add support for non-power-of-two mem chunks in verific importer"
This reverts commit 173aa27ca5 .
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2020-05-17 11:31:11 +02:00 |
Claire Wolf
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173aa27ca5
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Add support for non-power-of-two mem chunks in verific importer
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
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2020-05-14 14:38:13 +02:00 |
Eddie Hung
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5017ff4a97
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verific: ignore anonymous enums
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2020-04-30 07:48:47 -07:00 |
Eddie Hung
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97bfe65d3a
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verific: support VHDL enums too
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2020-04-27 15:17:13 -07:00 |
Eddie Hung
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dd5f206d9e
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verific: recover wiretype/enum attr as part of import_attributes()
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2020-04-27 08:43:54 -07:00 |
Eddie Hung
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b52eccef3a
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Revert "verific: import enum attributes from verific"
This reverts commit 5028e17f7d .
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2020-04-24 11:57:55 -07:00 |
Eddie Hung
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d3555c667c
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verific: do not assert if wire not found; warn instead
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2020-04-23 16:28:11 -07:00 |
Eddie Hung
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5028e17f7d
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verific: import enum attributes from verific
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2020-04-22 17:26:56 -07:00 |
Eddie Hung
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956ecd48f7
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kernel: big fat patch to use more ID::*, otherwise ID(*)
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2020-04-02 09:51:32 -07:00 |
Eddie Hung
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fdafb74eb7
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kernel: use more ID::*
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2020-04-02 07:14:08 -07:00 |
Claire Wolf
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2ce7a0d369
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Merge pull request #1667 from YosysHQ/clifford/verificnand
Add Verific support for OPER_REDUCE_NAND
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2020-01-30 19:55:53 +01:00 |
Claire Wolf
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60876ce183
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Merge pull request #1503 from YosysHQ/eddie/verific_help
`verific` pass to print help message when command syntax error
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2020-01-30 18:05:16 +01:00 |
Claire Wolf
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23c44afaed
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Add Verific support for OPER_REDUCE_NAND
Signed-off-by: Claire Wolf <clifford@clifford.at>
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2020-01-30 18:01:13 +01:00 |
Eddie Hung
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f443695a38
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Merge remote-tracking branch 'origin/master' into eddie/verific_help
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2020-01-27 10:34:10 -08:00 |
Eddie Hung
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d730bba6d2
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verific: no help() when no YOSYS_ENABLE_VERIFIC
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2020-01-27 10:32:18 -08:00 |
Eddie Hung
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7b445121cc
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verific: also unflatten for 'hierarchy' flow as per @cliffordwolf
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2020-01-27 10:15:22 -08:00 |
Eddie Hung
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cccc0ae112
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verific: unflatten struct ports
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2020-01-24 10:12:52 -08:00 |
Clifford Wolf
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22dd9f107c
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Send people to symbioticeda.com instead of verific.com
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-12-18 13:06:34 +01:00 |
Clifford Wolf
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db323685a4
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Add Verific support for SVA nexttime properties
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-11-22 16:11:56 +01:00 |
Clifford Wolf
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e93e4a7a2c
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Improve handling of verific primitives in "verific -import -V" mode
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-11-22 16:00:07 +01:00 |
Clifford Wolf
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6af0d03fae
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Add Verific SVA support for "always" properties
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-11-22 15:52:21 +01:00 |
Clifford Wolf
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55bda2b2c6
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Correctly treat empty modules as blackboxes in Verific
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-11-20 12:56:31 +01:00 |
Clifford Wolf
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f6ff311a1d
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Do not rename VHDL entities to "entity(impl)" when they are top modules
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-11-20 12:54:10 +01:00 |
Eddie Hung
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e2819ce31c
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Oops
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2019-11-19 13:25:38 -08:00 |
Eddie Hung
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84711f0e8c
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Print help message for verific pass
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2019-11-19 13:24:48 -08:00 |
Clifford Wolf
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84982b3083
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Improve naming scheme for (VHDL) modules imported from Verific
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-10-24 12:13:50 +02:00 |
Clifford Wolf
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d49c6b2cba
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Add "verific -L"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-10-24 09:14:03 +02:00 |
Clifford Wolf
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4033ff8c2e
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Fix handling of "restrict" in Verific front-end
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-10-21 12:39:28 +02:00 |
Clifford Wolf
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27d59dc055
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Fix erroneous ifndef-NDEBUG in verific.cc
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-08-17 14:49:55 +02:00 |
Clifford Wolf
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0c5db07cd6
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Fix various NDEBUG compiler warnings, closes #1255
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-08-13 13:29:03 +02:00 |
Clifford Wolf
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f54bf1631f
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Merge pull request #1258 from YosysHQ/eddie/cleanup
Cleanup a few barnacles across codebase
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2019-08-10 09:52:14 +02:00 |
Eddie Hung
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6d77236f38
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substr() -> compare()
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2019-08-07 12:20:08 -07:00 |
Eddie Hung
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48d0f99406
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stoi -> atoi
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2019-08-07 11:09:17 -07:00 |
Clifford Wolf
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9260e97aa2
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Automatically prune init attributes in verific front-end, fixes #1237
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-08-07 15:31:49 +02:00 |
Eddie Hung
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c11ad24fd7
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Use std::stoi instead of atoi(<str>.c_str())
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2019-08-06 16:45:48 -07:00 |
Eddie Hung
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046e1a5214
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Use State::S{0,1}
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2019-08-06 16:22:47 -07:00 |
Clifford Wolf
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fc462c8243
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Call "read_verilog" with -defer from "read"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-07-29 10:29:36 +02:00 |
Clifford Wolf
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36120fcc30
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Only support Symbiotic EDA flavored Verific
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-06-02 10:14:50 +02:00 |
Clifford Wolf
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2faa1d0e80
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Enable Verific flag veri_elaborate_top_level_modules_having_interface_ports, fixes #1055
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-30 10:04:26 +02:00 |
Eddie Hung
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c7d7d8ad1b
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For hier_tree::Elaborate() also include SV root modules (bind)
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2019-05-03 20:53:25 +02:00 |
Eddie Hung
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3ea54ec400
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Fix verific_parameters construction, use attribute to mark top netlists
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2019-05-03 20:53:25 +02:00 |
Eddie Hung
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a27b42e975
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WIP -chparam support for hierarchy when verific
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2019-05-03 20:53:25 +02:00 |
Eddie Hung
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0f1a4cc03c
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verific_import() changes to avoid ElaborateAll()
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2019-05-03 20:53:25 +02:00 |
Clifford Wolf
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7682629b79
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Add "read -verific" and "read -noverific"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-27 14:03:35 +01:00 |
Clifford Wolf
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c863796e9f
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Fix "verific -extnets" for more complex situations
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-26 14:17:46 +01:00 |
Clifford Wolf
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cebd21aa96
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Merge pull request #858 from YosysHQ/clifford/svalabels
Add support for using SVA labels in yosys-smtbmc console output
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2019-03-09 11:14:57 -08:00 |
Eddie Hung
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ee013fba54
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Update help message for -chparam
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2019-03-09 01:56:16 +00:00 |
Eddie Hung
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2aa3903757
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Add -chparam option to verific command
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2019-03-09 01:54:01 +00:00 |
Eddie Hung
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1dc060f32e
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Fix spelling
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2019-03-09 00:43:50 +00:00 |
Clifford Wolf
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cda37830b0
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Add hack for handling SVA labels via Verific
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-07 10:52:44 -08:00 |