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21 Commits

Author SHA1 Message Date
Eddie Hung e742478e1d Merge remote-tracking branch 'origin/master' into xc7dsp 2019-09-05 13:01:27 -07:00
Eddie Hung c4e5310823 Use a dummy box file if none specified 2019-08-28 20:58:55 -07:00
David Shah 269ff450f5 Add mul2dsp multiplier splitting rule and ECP5 mapping 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-08 18:42:09 +01:00
whitequark a91892bba4 cmp2lut: new techmap pass. 2019-01-02 07:53:31 +00:00
whitequark 9ef078848a gate2lut: new techlib, for converting Yosys gates to FPGA LUTs. 2018-12-05 17:13:27 +00:00
Clifford Wolf e7a984a4df Add dff2ff.v techmap file 2017-05-31 11:45:58 +02:00
Clifford Wolf 25c1f6e605 Added "prep" command 2015-10-14 22:46:41 +02:00
Clifford Wolf 7d3a3a3173 Added first help messages for cell types 2015-10-14 16:27:42 +02:00
Clifford Wolf e4ef000b70 Adjust makefiles to work with out-of-tree builds 
This is based on work done by Larry Doolittle
 2015-08-12 15:04:44 +02:00
Clifford Wolf 3ed4e34380 Added cells.lib 2015-01-16 15:50:42 +01:00
Clifford Wolf 1d96277f5d Added add_share_file Makefile macro 2015-01-08 00:23:18 +01:00
Clifford Wolf c64b1de11d Fixed build with SMALL=1 2014-12-30 11:41:24 +01:00
Clifford Wolf 7815f81c32 Added "synth" command 2014-09-14 16:09:06 +02:00
Clifford Wolf 312ee00c9e Added adff2dff.v (for techmap -share_map) 2014-08-07 16:14:38 +02:00
Clifford Wolf 1202f7aa4b Renamed "stdcells.v" to "techmap.v" 2014-07-31 02:32:00 +02:00
Clifford Wolf b17d6531c8 Added "make PRETTY=1" 2014-07-24 17:15:01 +02:00
Clifford Wolf 7aa2d746b7 Merged addition of SED makefile variable from github.com/Siesh1oo/yosys 
(see https://github.com/cliffordwolf/yosys/pull/28)
 2014-03-11 14:42:58 +01:00
Clifford Wolf db9cf544b8 Added techlibs/common/pmux2mux.v 2014-01-17 20:06:15 +01:00
Clifford Wolf 1afe6589df Renamed stdcells_sim.v to simcells.v and fixed blackbox.v 2013-11-24 20:44:00 +01:00
Clifford Wolf 0c91f890c9 Install simlib in datdir 2013-11-19 23:05:46 +01:00
Clifford Wolf 288ba9618a Moved common techlib files to techlibs/common 2013-09-15 11:52:57 +02:00