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14435 Commits

Author SHA1 Message Date
Martin Povišer 4c3203866f exec: Add missing newline 2024-08-07 13:02:00 +02:00
George Rennie b6ceff2aab peepopt clockgateff: add testcase 2024-08-07 10:21:52 +01:00
George Rennie 236c69bed4 clk2fflogic: run peepopt -formalclk before processing design 
* this attempts to rewrite clock gating patterns into a form that is
  less likely to introduce combinational loops with clk2fflogic

* can be disabled with -nopeepopt which is useful for testing
  clk2fflogic
 2024-08-07 10:14:04 +01:00
George Rennie 2cb3b6e9b8 peepopt: add formal only peepopt to rewrite latches to ffs in clock gates 
* this is gated behind the -formalclk flag, which also disables the other
  synthesis focused optimizations
 2024-08-07 10:01:45 +01:00
github-actions[bot] 669f8b18f0 Bump version 2024-08-07 00:18:20 +00:00
Miodrag Milanovic d08bf671b2 Next dev cycle 2024-08-06 09:48:35 +02:00
Miodrag Milanovic 80ba43d262 Release version 0.44 2024-08-06 09:42:28 +02:00
Miodrag Milanović e5d8505349
Merge pull request #4523 from YosysHQ/emil/no-lto-lld 
Makefile: no LTO and lld by default
 2024-08-06 09:08:09 +02:00
github-actions[bot] d2b5788674 Bump version 2024-08-06 00:18:14 +00:00
Emil J. Tywoniak eeecb54532 Makefile: no LTO and lld by default 2024-08-05 19:28:09 +02:00
N. Engelhardt 01b99972b4
Merge pull request #4518 from YosysHQ/micko/sim_signal_names 
Set ranges on exported wires in VCD and FST
 2024-08-05 15:03:59 +02:00
Miodrag Milanovic 6d98418f3d Set ranges on exported wires in VCD and FST 2024-08-02 15:23:00 +02:00
Roland Coeurjoly 7e34142965 Run nix build also on macos. Build with more logs 2024-07-30 22:47:30 +02:00
github-actions[bot] c788484679 Bump version 2024-07-30 00:18:19 +00:00
Miodrag Milanović 3e14e67374
Merge pull request #4500 from YosysHQ/micko/vhdl_mixcase 
VHDL is case insensitive, make sure netlist name is proper
 2024-07-29 16:44:13 +02:00
Emil J 92cac63845
Merge pull request #4344 from widlarizer/emil/keep_hierarchy 
cost: add keep_hierarchy pass with min_cost argument
 2024-07-29 16:33:08 +02:00
Miodrag Milanovic 405897a971 Update top value that is returned back to hierarchy pass 2024-07-29 15:50:38 +02:00
N. Engelhardt 9f869b265c
Merge pull request #4474 from tony-min-1/mchp 
Add PolarFire FPGA support
 2024-07-29 15:28:44 +02:00
N. Engelhardt 7c3666ff68
Merge pull request #4505 from YosysHQ/micko/ext_register 
Initialize extensions when Verific pass is registered
 2024-07-29 15:23:31 +02:00
Emil J e21dd292fc
Merge pull request #4502 from YosysHQ/emil/build-opt-levels 
Release build configuration improvements
 2024-07-29 15:13:52 +02:00
Emil J. Tywoniak af0c2fa659 Brewfile: add llvm for lld 2024-07-29 15:13:24 +02:00
Emil J 051d83205d
Merge pull request #4471 from georgerennie/hashlib_primes 
hashlib: Add some more primes
 2024-07-29 15:10:22 +02:00
Martin Povišer 61ae9f4e07
Merge pull request #4514 from YosysHQ/emil/proc_rom-src-test-2 
proc_rom: test src attribute on memories
 2024-07-29 13:58:19 +02:00
Emil J. Tywoniak 4b29f64142 cost: add model for techmapped cell count, keep_hierarchy pass with -min_cost parameter 2024-07-29 10:26:02 +02:00
Emil J 49eaa108a5
Merge pull request #4425 from YosysHQ/emil/doc-sigmap 
sigmap: comments
 2024-07-29 10:18:44 +02:00
Emil J. Tywoniak 01fd72520f proc_rom: test src attribute on memories 2024-07-29 10:13:45 +02:00
github-actions[bot] 960bca0196 Bump version 2024-07-27 00:17:35 +00:00
Martin Povišer ced1313193
Merge pull request #4510 from JamesTimothyMeech/patch-1 
Update interactive_investigation.rst
 2024-07-26 15:17:57 +02:00
James Meech 1c41db6978
Update interactive_investigation.rst 
The text starting at line 118 refers to proc twice but it should refer to opt and then to proc.
 2024-07-26 13:53:08 +01:00
N. Engelhardt dd3637f9f0
Merge pull request #4506 from povik/synthprop-formatting 
synthprop: Reformat the help
 2024-07-26 12:28:09 +02:00
N. Engelhardt 41b51c1ca9
Merge pull request #4503 from RCoeurjoly/vhdl_extension 
Guess VHDL frontend for both *.vhd and *vhdl files
 2024-07-26 10:44:10 +02:00
github-actions[bot] 610d27dc1c Bump version 2024-07-26 00:17:42 +00:00
Martin Povišer 7ee685a0b0 proc_rom: Set `src` on the emitted memory 2024-07-25 23:14:27 +01:00
Martin Povišer e063b96104 synthprop: Reformat the help 2024-07-25 11:43:58 +02:00
Miodrag Milanovic 9566709426 Initialize extensions when verific pass is registered 2024-07-25 11:25:17 +02:00
Emil J. Tywoniak 7cd27e1182 Makefile: remove accidental abc opt level override for wasi builds 2024-07-24 21:31:35 +02:00
Emil J. Tywoniak 29d53bc94a actions: try fix GITHUB_PATH 2024-07-24 19:50:34 +02:00
Emil J. Tywoniak ad47844bbf actions: macos install lld from llvm package 2024-07-24 18:32:04 +02:00
Roland Coeurjoly ce11ddbf21 Simplified run_frontend by using a lambda function for file extension checks and combining blif and eblif into a single condition. 2024-07-23 17:55:04 +02:00
Roland Coeurjoly 8c1431f373 Guess VHDL frontend for both *.vhd and *vhdl files 2024-07-23 17:01:57 +02:00
Roland Coeurjoly 5d0558932e Add llvmPackages.bintools to buildInputs, otherwise we get a linkage error 2024-07-22 20:11:08 +02:00
Emil J. Tywoniak a947572f38 Add lld to clang build environments and Dockerfile 2024-07-22 21:33:46 +02:00
Emil J. Tywoniak bf758b9097 Makefile: turn off LTO on gcc due to regression 2024-07-22 20:59:56 +02:00
Martin Povišer 118b2829db
Merge pull request #4499 from YosysHQ/emil/ast-comments 
ast: don't suggest use in external projects
 2024-07-19 10:33:50 +02:00
github-actions[bot] 28ebefda4a Bump version 2024-07-19 00:17:55 +00:00
Miodrag Milanovic c94aa719d9 VHDL is case insensitive, make sure netlist name is proper 2024-07-18 16:56:52 +02:00
Emil J. Tywoniak 72a0380da8 ast: don't suggest use in external projects 2024-07-18 16:37:14 +02:00
Emil J. Tywoniak 583db7b15e sigmap: comments 2024-07-18 16:02:11 +02:00
Martin Povišer 81df8557d9
Merge pull request #4494 from povik/install-bitpattern-h 
Makefile: do install `bitpattern.h`
 2024-07-18 15:50:58 +02:00
Martin Povišer 0cefe8a1e8 check: Skip detailed edge modeling if costly 2024-07-18 13:08:19 +02:00