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4238 Commits

Author SHA1 Message Date
Clifford Wolf d938ce7ab6 Merge branch 'master' of github.com:YosysHQ/yosys 2018-12-23 15:44:19 +01:00
Clifford Wolf e5eb3d2c8a
Merge pull request #757 from whitequark/manual_mem 
manual: document $meminit cell and memory_* passes
 2018-12-22 20:12:18 +01:00
whitequark 182d84ad54 manual: make description of $meminit ports match reality. 2018-12-21 23:04:31 +00:00
Clifford Wolf ee8a7589e0
Merge pull request #758 from whitequark/tcl_script_args 
tcl: add support for passing arguments to scripts
 2018-12-21 17:56:43 +01:00
Clifford Wolf 29a82acb2e
Merge pull request #759 from whitequark/memory_collect_init_x 
memory_collect: do not truncate 'x from \INIT
 2018-12-21 17:39:52 +01:00
whitequark 0c318e7db5 memory_collect: do not truncate 'x from \INIT. 
The semantics of an RTLIL constant that has less bits than its
declared bit width is zero padding. Therefore, if the output of
memory_collect will be used for simulation, truncating 'x from
the end of \INIT will produce incorrect simulation results.
 2018-12-21 02:01:27 +00:00
whitequark c04908c997 manual: fix typos. 2018-12-20 07:59:40 +00:00
whitequark 2ca237e086 tcl: add support for passing arguments to scripts. 2018-12-20 07:32:24 +00:00
whitequark a9ff81dd82 manual: document $meminit cell and memory_* passes. 2018-12-20 04:54:31 +00:00
Clifford Wolf 93d44bb9a6
Merge pull request #752 from Icenowy/anlogic-lut-cost 
Anlogic: let LUT5/6 have more cost than LUT4-
 2018-12-19 19:52:31 +01:00
Clifford Wolf c98d44ac12
Merge pull request #753 from Icenowy/anlogic-makefile-fix 
anlogic: fix Makefile.inc
 2018-12-19 19:51:10 +01:00
Clifford Wolf 4d84a456dc
Merge pull request #749 from Icenowy/anlogic-dram-fix 
anlogic: fix dbits of Anlogic Eagle DRAM16X4
 2018-12-19 19:48:54 +01:00
Icenowy Zheng 3993ba71f7 anlogic: fix Makefile.inc 
During the addition of DRAM inferring support, the installation of
eagle_bb.v is accidentally removed.

Fix this issue.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
 2018-12-19 10:23:58 +08:00
Icenowy Zheng c9513c695a Anlogic: let LUT5/6 have more cost than LUT4- 
According to the datasheet of Anlogic Eagle FPGAs, The LUTs natively
in an Anlogic FPGA is LUT4 (in MSLICEs) and "Enhanced LUT5" (in
LSLICEs). An "Enhanced LUT5" can be divided into two LUT4s.

So a LUT5 will cost around 2x resource of a LUT4, and a LUT6 will cost
2x resource of a LUT5.

Change the -lut parameter passed to the abc command to pass this cost
info to the ABC process.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
 2018-12-19 09:36:53 +08:00
Clifford Wolf 23bb77867f Minor style fixes 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-18 20:02:39 +01:00
Clifford Wolf 2d73e1b60a
Merge pull request #748 from makaimann/add-btor-ops 
Add btor ops for $mul, $div, $mod and $concat
 2018-12-18 19:59:29 +01:00
Clifford Wolf eddf075d93
Merge pull request #751 from daveshah1/fix_589 
memory_dff: Fix typo when checking init value
 2018-12-18 19:55:42 +01:00
David Shah 2b16d4ed3d memory_dff: Fix typo when checking init value 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-12-18 17:40:01 +00:00
Clifford Wolf fdf7c42181 Fix segfault in AST simplify 
(as proposed by Dan Gisselquist)

Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-18 17:49:38 +01:00
Clifford Wolf 3d671630e2 Improve src tagging (using names and attrs) of cells and wires in verific front-end 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-18 16:01:22 +01:00
Icenowy Zheng 7854d5ba21 anlogic: fix dbits of Anlogic Eagle DRAM16X4 
The dbits of DRAM16X4 is wrong set to 2, which leads to waste of DRAM
bits.

Fix the dbits number in the RAM configuration.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
 2018-12-18 14:38:44 +08:00
makaimann abf5930a33 Add btor ops for $mul, $div, $mod and $concat 2018-12-17 10:45:17 -08:00
Clifford Wolf 847fd36077
Merge pull request #746 from Icenowy/anlogic-dram 
Support for DRAM inferring on Anlogic FPGAs
 2018-12-17 17:16:10 +01:00
Clifford Wolf 3b4290a1b8
Merge pull request #742 from whitequark/changelog 
Update CHANGELOG to mention my improvements
 2018-12-17 16:35:56 +01:00
Clifford Wolf 97b49d6e45
Merge pull request #741 from whitequark/ilang_slice_sigspec 
read_ilang: allow slicing all sigspecs, not just wires
 2018-12-17 16:29:25 +01:00
Clifford Wolf ce701fd334
Merge pull request #744 from whitequark/write_verilog_$shift 
write_verilog: handle the $shift cell
 2018-12-17 16:26:57 +01:00
Icenowy Zheng d53a2bd1d3 anlogic: add support for Eagle Distributed RAM 
The MSLICEs on the Eagle series of FPGA can be configured as Distributed
RAM.

Enable to synthesis to DRAM.

As the Anlogic software suite doesn't support any 'bx to exist in the
initializtion data of DRAM, do not enable the initialization support of
the inferred DRAM.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
 2018-12-17 23:20:40 +08:00
Icenowy Zheng 634d7d1c14 Revert "Leave only real black box cells" 
This reverts commit 43030db5ff.

For a synthesis tool, generating EG_LOGIC cells are a good choice, as
they can be furtherly optimized when PnR, although sometimes EG_LOGIC is
not as blackbox as EG_PHY cells (because the latter is more close to the
hardware implementation).

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
 2018-12-17 23:20:40 +08:00
Clifford Wolf dc6e63d8cd
Merge pull request #745 from YosysHQ/revert-714-abc_preserve_naming 
Revert "Proof-of-concept: preserve naming through ABC using dress"
 2018-12-16 21:27:56 +01:00
Clifford Wolf 2641a3089b
Revert "Proof-of-concept: preserve naming through ABC using dress" 2018-12-16 21:27:31 +01:00
whitequark ca866d384e write_verilog: handle the $shift cell. 
The implementation corresponds to the following Verilog, which is
lifted straight from simlib.v:

    module \\$shift (A, B, Y);

    parameter A_SIGNED = 0;
    parameter B_SIGNED = 0;
    parameter A_WIDTH = 0;
    parameter B_WIDTH = 0;
    parameter Y_WIDTH = 0;

    input [A_WIDTH-1:0] A;
    input [B_WIDTH-1:0] B;
    output [Y_WIDTH-1:0] Y;

    generate
        if (B_SIGNED) begin:BLOCK1
            assign Y = $signed(B) < 0 ? A << -B : A >> B;
        end else begin:BLOCK2
            assign Y = A >> B;
        end
    endgenerate

    endmodule
 2018-12-16 18:46:32 +00:00
whitequark 9f5c7017ff Update CHANGELOG. 2018-12-16 18:26:00 +00:00
whitequark 4effb38e6d read_ilang: allow slicing sigspecs. 2018-12-16 17:53:26 +00:00
Clifford Wolf ddff75b60a
Merge pull request #736 from whitequark/select_assert_list 
select: print selection if a -assert-* flag causes an error
 2018-12-16 16:45:49 +01:00
whitequark f6412d7109 select: print selection if a -assert-* flag causes an error. 2018-12-16 15:44:29 +00:00
Clifford Wolf 5fa5dbbdda Rename "fine:" label to "map:" in "synth_ice40" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-16 16:36:19 +01:00
Clifford Wolf 4c5173045b
Merge pull request #704 from webhat/feature/fix-awk 
Using awk rather than gawk
 2018-12-16 16:31:37 +01:00
whitequark fccaa25ec1 write_verilog: add a missing newline. 2018-12-16 15:22:34 +00:00
Clifford Wolf ac27a5a737
Merge pull request #738 from smunaut/issue_737 
verilog_parser: Properly handle recursion when processing attributes
 2018-12-16 16:05:14 +01:00
Clifford Wolf 0d9c850a07
Merge pull request #735 from daveshah1/trifixes 
deminout fixes
 2018-12-16 16:02:21 +01:00
Clifford Wolf 1e1452c7ff
Merge pull request #739 from whitequark/patch-1 
Add .editorconfig file
 2018-12-16 16:01:13 +01:00
whitequark 8f359cf1ff
Add .editorconfig file. 
See https://editorconfig.org/ for details.
 2018-12-16 14:57:43 +00:00
Clifford Wolf f53e19cc71 Fix equiv_opt indenting 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-16 15:57:28 +01:00
Clifford Wolf 2a681909df
Merge pull request #724 from whitequark/equiv_opt 
equiv_opt: new command, for verifying optimization passes
 2018-12-16 15:54:26 +01:00
Clifford Wolf a2154c1be0
Merge pull request #734 from grahamedgecombe/fix-shuffled-bram-initdata 
memory_bram: Fix initdata bit order after shuffling
 2018-12-16 15:53:44 +01:00
Clifford Wolf ceffa66dbd
Merge pull request #730 from smunaut/ffssr_dont_touch 
ice40: Honor the "dont_touch" attribute in FFSSR pass
 2018-12-16 15:50:42 +01:00
Clifford Wolf f481ad4d44
Merge pull request #729 from whitequark/write_verilog_initial 
write_verilog: correctly map RTLIL `sync init`
 2018-12-16 15:50:16 +01:00
Clifford Wolf 0c69f1d777
Merge pull request #725 from olofk/ram4k-init 
Only use non-blocking assignments of SB_RAM40_4K for yosys
 2018-12-16 15:42:04 +01:00
Clifford Wolf a1fb5b1e4b
Merge pull request #714 from daveshah1/abc_preserve_naming 
Proof-of-concept: preserve naming through ABC using dress
 2018-12-16 15:41:30 +01:00
Clifford Wolf 9522eee02f
Merge pull request #723 from whitequark/synth_ice40_map_gates 
synth_ice40: split `map_gates` off `fine`
 2018-12-16 15:30:08 +01:00