ec8d7b1c68
abc9_ops -prep_hier to unmap entire module
2023-05-25 18:42:08 +01:00
52c8c28d2c
Add recover_names pass to recover names post-mapping
2023-05-25 10:55:07 +02:00
ad2b04d63a
sim: Fix cosimulation with nested modules having unconnected inputs
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When assigning values to input ports of nested modules in cosimulation,
sim needs to find the actual driver of the signal to perform the
assignment. The existing code didn't handle unconnected inputs in that
scenario.
2023-05-18 16:50:11 +02:00
693c609eec
Merge branch 'YosysHQ:master' into main/issue2525
2023-05-16 21:21:32 -07:00
665e0f6131
remove new line per maintainer request
2023-05-17 04:20:13 +00:00
acfdc5cc42
Merge pull request #3755 from RTLWorks/muthu/issue3498
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[YOSYS] Issue #3498 - Fix Synopsys style unquoted Liberty style
2023-05-15 16:34:35 +02:00
c855502bd5
Update passes/techmap/libparse.cc
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Allow Liberty canonical identifier including double quotes in if-body and pass-through for Synopsys-style unquoted identifiers issue#3498
Co-authored-by: Aki <201479+lethalbit@users.noreply.github.com>
2023-05-09 06:40:21 -07:00
226a224640
Merge pull request #3749 from lethalbit/aki/plugin-stuff
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Updated the `plugin` command to better handle paths
2023-05-09 08:46:02 +02:00
266036c6f9
Merge pull request #3756 from YosysHQ/krys/sim_writeback
2023-05-08 16:21:24 +02:00
ec56e625f4
Merge pull request #3742 from jix/fix_rename_witness_cell_renames
2023-05-08 16:13:28 +02:00
5a4e72f57a
Fix sim writeback check for yw_cosim
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Writeback of simulation state into initial state was only working for `run()` and `run_cosim_fst()`.
This change moves the writeback into the `write_output_files()` function so that all simulation modes work with the writeback option.
2023-05-08 13:13:09 +12:00
17cfc969dd
[YOSYS] Issue #3498 - Fix Synopsys style unquoted Liberty style function body parsing with unittest
2023-05-06 23:37:47 -07:00
4251d37f4f
Merge pull request #3610 from YosysHQ/synthprop
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Synthesizable properties
2023-05-05 11:03:09 +02:00
81e089cb60
[YOSYS-2525] fix read_liberty newline handling #2525
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- newlines can be allowed in function parsing
2023-05-04 22:30:27 -07:00
bb240665b7
plugin: shuffled the `#ifdef WITH_PYTHON`'s around to un-tangle the code and pulled out the check for the `.py` extension so it will complain if you try to load a python extension without python support
2023-05-03 03:35:55 -04:00
572c8df9a8
plugin: Re-vamped how plugin lookup was done to make it more consistent with the rest of yosys, and prevented a case where you could end up with `.so.so` on the end
2023-05-03 02:22:46 -04:00
7bff8b63b3
rename: Fix renaming cells in -witness mode
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This was renaming cells while iterating over them which would always
cause an assertion failure. Apparently having to rename cells to make
all witness signals public is rarely required, so this slipped through.
2023-04-25 12:39:00 +02:00
8611429237
ABC9: Cell Port Bug Patch ( #3670 )
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* ABC9: RAMB36E1 Bug Patch
* Add simplified testcase
* Also fix xaiger writer for under-width output ports
* Remove old testcase
* Missing top-level input port
* Fix tabs
---------
Co-authored-by: Eddie Hung <eddie@fpgeh.com>
2023-04-22 16:24:36 -07:00
57897927ff
stat: pass down quiet arg
2023-02-28 17:12:55 +01:00
21e87f7986
Merge pull request #3646 from YosysHQ/lofty/fix-3591
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muxcover: do not add decode muxes with x inputs
2023-02-27 16:26:57 +01:00
1c667fab2b
Merge pull request #3672 from jix/yw-cosim-hierarchy-fixes
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sim: For yw cosim, drive parent module's signals for input ports
2023-02-15 13:45:00 +01:00
ec94703619
Merge pull request #2995 from georgerennie/cover_precond
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chformal: Add -coverenable option
2023-02-14 17:46:31 +01:00
85f611fb23
Merge pull request #3126 from georgerennie/equiv_make_assertions
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equiv_make: Add -make_assert option
2023-02-14 17:15:55 +01:00
b636af9751
chformal: Note about using -coverenable with the Verific frontend
2023-02-14 17:10:43 +01:00
550a5b7b6b
Update license
2023-02-13 17:23:26 +01:00
713b7d3e26
added support for latched output reset
2023-02-13 17:23:26 +01:00
131b557727
Initial implementation of synthesizable assertions
2023-02-13 17:23:26 +01:00
1698202ccc
sim: For yw cosim, drive parent module's signals for input ports
2023-02-13 12:26:06 +01:00
5f33c0e0b2
Updated changelog
2023-02-08 10:11:47 +01:00
417fadbefd
Merge pull request #3625 from povik/show_cleanup
2023-02-06 16:11:26 +01:00
419f91a2b9
add option to fsm_detect to ignore self-resetting
2023-01-30 16:12:53 +01:00
ecfa7e9fbc
add pmux option to bmuxmap for better fsm detection with verific frontend
2023-01-30 16:12:53 +01:00
822c7b0341
muxcover: do not add decode muxes with x inputs
2023-01-26 05:19:45 +00:00
afac3f2c76
formalff: Fix crash with _NOT_ gates in -hierarchy mode
2023-01-25 12:55:29 +01:00
8180cc4325
Merge pull request #3624 from jix/sim_yw
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Changes to support SBY trace generation with the sim command
2023-01-23 16:55:17 +01:00
245884a101
Merge pull request #3629 from YosysHQ/micko/clang_fixes
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Fixes for some of clang scan-build detected issues
2023-01-23 16:24:22 +01:00
bfacaddca8
show: Remove left-in debug log_warning
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Signed-off-by: gatecat <gatecat@ds0.me>
2023-01-23 13:54:07 +01:00
bfc3c20cfb
Improve splitcells pass
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2023-01-18 00:31:29 +01:00
6574553189
Fixes for some of clang scan-build detected issues
2023-01-17 12:58:08 +01:00
f9e30ee5e0
passes: show: s/pos/bitpos/ for readability
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Signed-off-by: Martin Povišer <povik@cutebit.org>
2023-01-13 19:57:24 +01:00
314b864205
passes: show: Reuse string parts in generation of portboxes
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Signed-off-by: Martin Povišer <povik@cutebit.org>
2023-01-13 19:57:24 +01:00
61abca10a3
passes: show: Touch chunk iteration in gen_portbox
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Signed-off-by: Martin Povišer <povik@cutebit.org>
2023-01-13 19:57:24 +01:00
60318a5cd8
passes: show: Label no_signode flag
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Label the flag and rearrange the control flow a bit.
Signed-off-by: Martin Povišer <povik@cutebit.org>
2023-01-13 19:57:24 +01:00
8b1f5fba62
passes: show: Simplify wire bit range logic
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Signed-off-by: Martin Povišer <povik@cutebit.org>
2023-01-13 19:57:24 +01:00
ad149cc42a
passes: show: Factor out 'join_label_pieces'
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In two places, we are joining label pieces by a '|' separator. We go
about it by putting the separator behind each entry, then removing the
trailing separator in a final fixup pass on the built string. For easier
reading, replace those occurrences by a new factored-out
'join_label_pieces' function.
Signed-off-by: Martin Povišer <povik@cutebit.org>
2023-01-13 19:57:24 +01:00
5848790835
passes: show: Label signed_suffix flag
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To make it easier to follow what's going on.
Signed-off-by: Martin Povišer <povik@cutebit.org>
2023-01-13 19:57:24 +01:00
13700e12e5
passes: show: s/idx/dot_idx/ for readability
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Signed-off-by: Martin Povišer <povik@cutebit.org>
2023-01-13 19:57:24 +01:00
e3709ce776
passes: show: Fix portbox bit ranges in case of driven signals
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When the 'show' pass generates portboxes to detail the connection of
cell ports to wires, it has special handling of signal chunk
repetitions, but those repetitions are not accounted for in the
displayed bit range in case of cell outputs. Fix that, and so bring it
into consistence with the behavior on cell inputs.
So, taking for example the following Verilog snippet,
module DRIVER (Q);
output [7:0] Q;
assign Q = 8'b10101010;
endmodule
module main;
wire w;
DRIVER driver(.Q({8{w}}));
endmodule
make the show pass display '7:0 - 8x 0:0' in the driver-to-w portbox
instead of '7:7 - 8x 0:0' which it displayed formerly.
Signed-off-by: Martin Povišer <povik@cutebit.org>
2023-01-13 19:57:24 +01:00
d6c7aa0e3d
sim/formalff: Clock handling for yw cosim
2023-01-11 18:07:16 +01:00
7ddec5093f
sim: Improvements and fixes for yw cosim
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* Fixed $cover handling
* Improved sparse memory handling when writing traces
* JSON summary output
2023-01-11 18:07:16 +01:00
Eddie Hung
gatecat
Jannis Harder
Muthiah Annamalai (முத்து அண்ணாமலை)
Muthu Annamalai
Miodrag Milanović
N. Engelhardt
Krystine Sherwin
Muthu Annamalai
Aki Van Ness
Benjamin Barzen
Lofty
Claire Xenia Wolf
Martin Povišer