riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
14,040 Commits 92 Branches 49 Tags 39 MiB
Commit Graph

14040 Commits

Author SHA1 Message Date
Martin Povišer 0d5e9acd34 README.md: s/write_ilang/write_rtlil/ 
It's my understanding write_ilang is deprecated so best no to mention it
in the README.
 2023-07-10 12:57:05 +02:00
Martin Povišer eb083c5d4b extract_counter: Update help and comments after UP/DOWN support 
Commit fec7dc5c should have added support for up counters so update
the help and comments accordingly.
 2023-07-10 12:45:03 +02:00
Martin Povišer 8839d7fa5a cellaigs: Fix the case of $_NMUX_ cells 
Later on there's a

  if (cell->type == ID($_NMUX_))

but that code was unreachable until now.
 2023-07-10 12:45:03 +02:00
Martin Povišer 78d13d1956 Mention 'bwmuxmap' in 'write_firrtl' help 
The FIRRTL backend does call into the 'bwmuxmap' pass but omits it in
the help message.
 2023-07-10 12:45:03 +02:00
Martin Povišer c0b1a7daa4 Drop stray 'cellaigs.h' include from backend passes 
This include seems to have been copied over from the JSON backend where
AIG models are sometimes inserted into the JSON output, but these other
backends don't do anything with AIG.
 2023-07-10 12:45:03 +02:00
Martin Povišer 7c6cc4c40b tests: Fix invocation of 'help -cells' 
There's no such thing as 'help -celltypes' and there probably never was.
 2023-07-10 12:42:09 +02:00
Martin Povišer 06256c0c00 Slightly adjust the wording of "write_blif" help 2023-07-10 12:41:43 +02:00
N. Engelhardt 57de249881 memory_libmap: print additional debug messages when no valid mapping is found 2023-07-06 18:54:32 +02:00
Martin Povišer 991bff00f1 Makefile: install cellaigs.h header 2023-07-04 00:50:38 +02:00
N. Engelhardt 14d50a176d
Merge pull request #3676 from nakengelhardt/dfflegalize_scratchpad_minarg 2023-07-03 17:15:21 +02:00
N. Engelhardt a6be7b4751 memory_libmap: add debug messages for some reasons for rejecting mappings 2023-06-29 14:08:31 +02:00
github-actions[bot] b5b0b7e839 Bump version 2023-06-29 00:18:55 +00:00
N. Engelhardt 7542146fc5 memory_libmap: print message about attributes forcing ram kind 2023-06-28 17:48:20 +02:00
Charlotte eb397592f0 cxxrtl: add `$divfloor`. 2023-06-28 15:27:06 +01:00
Jannis Harder 911a76affa
Merge pull request #3825 from jix/abc-fold-s 2023-06-28 13:05:30 +02:00
Jannis Harder a7bccdfe8d Update ABC version 2023-06-28 11:20:44 +02:00
Jannis Harder 596da3f2a6
Merge pull request #3815 from charlottia/py312-syntax 2023-06-26 16:36:58 +02:00
Jannis Harder 6be5f6449c
Merge pull request #3816 from jix/smtbmc-cover-keepgoing 2023-06-26 16:35:52 +02:00
Jannis Harder b87af9cec0
Merge pull request #3817 from jix/constant_drive_conflict 2023-06-26 16:19:50 +02:00
github-actions[bot] 2310a0ea9a Bump version 2023-06-25 00:21:16 +00:00
Miodrag Milanović 9ba7170919
Merge pull request #3818 from nakengelhardt/nak/verific_import_mem_access_src_loc 
verific: import src attribute on $memrd/$memwr cells
 2023-06-24 10:42:45 +02:00
N. Engelhardt 21686f0d9d verific: import src attribute on $memrd/$memwr cells 2023-06-23 19:41:36 +02:00
Jannis Harder a07f8ac38a check: Also check for conflicts with constant drivers 2023-06-23 18:07:28 +02:00
Jannis Harder f9744fdfcd smtbmc: Make cover mode respect --keep-going 
As cover mode by default stops looking for further traces when an
assertion fails, it should respect --keep-going.
 2023-06-23 10:27:38 +02:00
Charlotte 3f29bdbbc5 smt2: py3.12+: avoid SyntaxWarning. 
Python 3.12 emits a SyntaxWarning when encountering invalid escape
sequences.  They still parse as expected.  Marking these raw produces
the same result without the warnings.
 2023-06-23 14:40:02 +10:00
Miodrag Milanović f9257d3192
Merge pull request #3811 from YosysHQ/micko/defaultvalue 
Use defaultvalue for init values of input ports
 2023-06-22 09:39:45 +02:00
github-actions[bot] 8f7a9a0b66 Bump version 2023-06-22 00:17:44 +00:00
Claire Xen 51e627686a
Merge pull request #3812 from charlottia/iterator-invalidation 
proc_prune: avoid using invalidated iterator
 2023-06-21 14:46:25 +02:00
Miodrag Milanovic aff0065646 Use defaultvalue for init values of input ports 2023-06-21 13:21:34 +02:00
Charlotte 63e4114233 proc_prune: avoid using invalidated iterator 
An `std::vector<T>::reverse_iterator` stores the
`std::vector<T>::iterator` which points to the (forwards-ordered)
*following* item.  Thus while `vec.rbegin()` dereferences to the final
item of `vec`, the iterator it wraps (`vec.rbegin().base()`) is equal to
`vec.end()`.

In the remove case here, we advance `it` (backwards), erasing the item
we just advanced past by grabbing its (pre-increment) base
forward-iterator and subtracting 1.

The iterator maths here is obviously all OK, but the forward-iterator
that `it` wraps post-increment actually points to the item we just
removed.  That iterator was invalidated by the `erase()` call.

That this works anyway is (AFAICT) some combination of luck and/or
promises that aren't part of the C++ spec, but MSVC's debug iterator
support picks this up.

`erase()` returns the new iterator that follows the item just erased,
which happens to be the exact one we want our reverse-iterator to wrap
for the next loop; we get a fresh iterator to the same base, now without
the preceding item.
 2023-06-21 19:53:08 +10:00
N. Engelhardt 941fa70ce1
Merge pull request #3809 from YosysHQ/nak/show_escape 2023-06-21 10:38:32 +02:00
N. Engelhardt f573aebdd3
Merge pull request #3810 from charlottia/docs-celllib-minor 2023-06-21 10:34:59 +02:00
Charlotte 0c0171bd60 docs: RD_DATA is an output, not input 2023-06-21 17:21:04 +10:00
github-actions[bot] 104edb4587 Bump version 2023-06-21 00:17:27 +00:00
Claire Xen 48cafd5ccf
Merge pull request #1489 from YosysHQ/clifford/ediflsbidx 
Add "write_edif -lsbidx"
 2023-06-20 17:58:44 +02:00
N. Engelhardt 9c7f0e7670 show: truncate very long module names 2023-06-20 12:53:56 +02:00
N. Engelhardt 22c9237716 show: escape angle brackets 2023-06-20 11:17:12 +02:00
Clifford Wolf cff3195caa Improve EDIF lib_cell_ports scan 2023-06-20 10:42:05 +02:00
Clifford Wolf fb9e12761b Add "write_edif -lsbidx" 2023-06-20 10:40:15 +02:00
github-actions[bot] 25954715f0 Bump version 2023-06-20 00:16:06 +00:00
Jannis Harder d3ee4eba5b
Merge pull request #3797 from charlottia/one-length-memories 2023-06-19 16:21:06 +02:00
N. Engelhardt 3fa83ca195
Merge pull request #3808 from YosysHQ/krys/docs 2023-06-19 12:12:56 +02:00
Krystine Sherwin d1b86d2fcf
docs: reflow memory map 
Move additional notes up to the top and give it its own section.  Also reformat some paragraphs, and turn some bullet points into paragraphs.
Split supported patterns section into some kind of grouping.
Currently:
- SDP
- single-port RAM
- reset patterns
- asymmetric
- TDP
 2023-06-19 12:05:51 +12:00
Charlotte Connor c9d31c3c87 smt2: abits needs to be at least 1 for BitVec 
BitVecs need a minimum length of 1; we zero-fill any extra bits in the
extend_u0() calls which works perfectly.
 2023-06-13 15:01:45 +10:00
github-actions[bot] 8b2a001021 Bump version 2023-06-13 00:17:19 +00:00
Jannis Harder 06f06c7be2
Merge pull request #3801 from jix/witness-aiw2yw-xbits 2023-06-12 16:12:39 +02:00
Miodrag Milanović a310bd2d23
Merge pull request #3802 from YosysHQ/micko/build_full 
Improve Verific usage in plugins
 2023-06-12 16:07:06 +02:00
Miodrag Milanović 8b74e8ad3a
Merge pull request #3796 from YosysHQ/micko/update_abc 
Update ABC to latest
 2023-06-12 16:06:56 +02:00
Miodrag Milanovic 34a6bef768 link verific where appropriate and link full archives 2023-06-12 10:01:35 +02:00
Miodrag Milanovic 75cf79588e Add ability for user plugin to add new verific log callback 2023-06-12 10:01:01 +02:00