mirror of https://github.com/YosysHQ/yosys.git
extract_counter: Implement extracting up counters
This commit is contained in:
R. Ou
parent
940bab6841
commit
fec7dc5c9e
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@ -90,6 +90,7 @@ bool is_unconnected(const RTLIL::SigSpec& port, ModIndex& index)
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struct CounterExtraction
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{
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int width; //counter width
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bool count_is_up; //count up (else down)
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RTLIL::Wire* rwire; //the register output
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bool has_reset; //true if we have a reset
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bool has_ce; //true if we have a clock enable
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@ -105,7 +106,7 @@ struct CounterExtraction
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bool has_pout; //whether parallel output is used
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RTLIL::Cell* count_mux; //counter mux
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RTLIL::Cell* count_reg; //counter register
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RTLIL::Cell* underflow_inv; //inverter reduction for output-underflow detect
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RTLIL::Cell* overflow_cell; //cell for counter overflow (either inverter reduction or $eq)
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pool<ModIndex::PortInfo> pouts; //Ports that take a parallel output from us
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};
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@ -115,6 +116,7 @@ struct CounterExtractionSettings
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int maxwidth;
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int minwidth;
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bool allow_arst;
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int allowed_dirs; //0 = down, 1 = up, 2 = both
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};
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//attempt to extract a counter centered on the given adder cell
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@ -128,43 +130,128 @@ int counter_tryextract(
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{
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SigMap& sigmap = index.sigmap;
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//Check if counter is an appropriate size
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int a_width = cell->getParam(ID(A_WIDTH)).as_int();
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extract.width = a_width;
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if( (a_width < settings.minwidth) || (a_width > settings.maxwidth) )
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return 1;
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//Second input must be a single bit
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int b_width = cell->getParam(ID(B_WIDTH)).as_int();
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if(b_width != 1)
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return 2;
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//Both inputs must be unsigned, so don't extract anything with a signed input
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bool a_sign = cell->getParam(ID(A_SIGNED)).as_bool();
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bool b_sign = cell->getParam(ID(B_SIGNED)).as_bool();
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if(a_sign || b_sign)
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return 3;
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//To be a counter, one input of the ALU must be a constant 1
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//TODO: can A or B be swapped in synthesized RTL or is B always the 1?
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const RTLIL::SigSpec b_port = sigmap(cell->getPort(ID::B));
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if(!b_port.is_fully_const() || (b_port.as_int() != 1) )
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return 4;
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//BI and CI must be constant 1 as well
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const RTLIL::SigSpec bi_port = sigmap(cell->getPort(ID(BI)));
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if(!bi_port.is_fully_const() || (bi_port.as_int() != 1) )
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return 5;
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const RTLIL::SigSpec ci_port = sigmap(cell->getPort(ID(CI)));
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if(!ci_port.is_fully_const() || (ci_port.as_int() != 1) )
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return 6;
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//CO and X must be unconnected (exactly one connection to each port)
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if(!is_unconnected(sigmap(cell->getPort(ID(CO))), index))
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return 7;
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if(!is_unconnected(sigmap(cell->getPort(ID(X))), index))
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return 8;
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//true if $alu is performing A - B, else A + B
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bool alu_is_subtract;
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//BI and CI must be both constant 0 or both constant 1 as well
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const RTLIL::SigSpec bi_port = sigmap(cell->getPort(ID(BI)));
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const RTLIL::SigSpec ci_port = sigmap(cell->getPort(ID(CI)));
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if(bi_port.is_fully_const() && bi_port.as_int() == 1 &&
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ci_port.is_fully_const() && ci_port.as_int() == 1)
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{
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alu_is_subtract = true;
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}
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else if(bi_port.is_fully_const() && bi_port.as_int() == 0 &&
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ci_port.is_fully_const() && ci_port.as_int() == 0)
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{
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alu_is_subtract = false;
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}
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else
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{
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return 5;
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}
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//false -> port B connects to value
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//true -> port A connects to value
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bool alu_port_use_a = false;
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if(alu_is_subtract)
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{
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const int a_width = cell->getParam(ID(A_WIDTH)).as_int();
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const int b_width = cell->getParam(ID(B_WIDTH)).as_int();
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const RTLIL::SigSpec b_port = sigmap(cell->getPort(ID::B));
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// down, cnt <= cnt - 1
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if (b_width == 1 && b_port.is_fully_const() && b_port.as_int() == 1)
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{
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// OK
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alu_port_use_a = true;
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extract.count_is_up = false;
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}
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// up, cnt <= cnt - -1
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else if (b_width == a_width && b_port.is_fully_const() && b_port.is_fully_ones())
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{
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// OK
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alu_port_use_a = true;
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extract.count_is_up = true;
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}
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// ???
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else
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{
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return 2;
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}
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}
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else
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{
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const int a_width = cell->getParam(ID(A_WIDTH)).as_int();
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const int b_width = cell->getParam(ID(B_WIDTH)).as_int();
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const RTLIL::SigSpec a_port = sigmap(cell->getPort(ID::A));
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const RTLIL::SigSpec b_port = sigmap(cell->getPort(ID::B));
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// down, cnt <= cnt + -1
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if (b_width == a_width && b_port.is_fully_const() && b_port.is_fully_ones())
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{
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// OK
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alu_port_use_a = true;
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extract.count_is_up = false;
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}
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else if (a_width == b_width && a_port.is_fully_const() && a_port.is_fully_ones())
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{
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// OK
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alu_port_use_a = false;
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extract.count_is_up = false;
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}
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// up, cnt <= cnt + 1
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else if (b_width == 1 && b_port.is_fully_const() && b_port.as_int() == 1)
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{
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// OK
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alu_port_use_a = true;
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extract.count_is_up = true;
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}
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else if (a_width == 1 && a_port.is_fully_const() && a_port.as_int() == 1)
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{
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// OK
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alu_port_use_a = false;
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extract.count_is_up = true;
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}
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// ???
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else
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{
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return 2;
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}
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}
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if (extract.count_is_up && settings.allowed_dirs == 0)
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return 26;
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if (!extract.count_is_up && settings.allowed_dirs == 1)
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return 26;
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//Check if counter is an appropriate size
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int count_width;
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if (alu_port_use_a)
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count_width = cell->getParam(ID(A_WIDTH)).as_int();
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else
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count_width = cell->getParam(ID(B_WIDTH)).as_int();
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extract.width = count_width;
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if( (count_width < settings.minwidth) || (count_width > settings.maxwidth) )
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return 1;
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//Y must have exactly one connection, and it has to be a $mux cell.
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//We must have a direct bus connection from our Y to their A.
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const RTLIL::SigSpec aluy = sigmap(cell->getPort(ID::Y));
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@ -178,30 +265,43 @@ int counter_tryextract(
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if(!is_full_bus(aluy, index, cell, ID::Y, count_mux, ID::A))
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return 11;
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//B connection of the mux is our underflow value
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const RTLIL::SigSpec underflow = sigmap(count_mux->getPort(ID::B));
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if(!underflow.is_fully_const())
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return 12;
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extract.count_value = underflow.as_int();
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if (extract.count_is_up)
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{
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//B connection of the mux must be 0
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const RTLIL::SigSpec underflow = sigmap(count_mux->getPort(ID::B));
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if(!(underflow.is_fully_const() && underflow.is_fully_zero()))
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return 12;
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}
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else
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{
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//B connection of the mux is our underflow value
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const RTLIL::SigSpec underflow = sigmap(count_mux->getPort(ID::B));
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if(!underflow.is_fully_const())
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return 12;
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extract.count_value = underflow.as_int();
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}
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//S connection of the mux must come from an inverter (need not be the only load)
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//S connection of the mux must come from an inverter if down, eq if up
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//(need not be the only load)
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const RTLIL::SigSpec muxsel = sigmap(count_mux->getPort(ID(S)));
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extract.outsig = muxsel;
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pool<Cell*> muxsel_conns = get_other_cells(muxsel, index, count_mux);
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Cell* underflow_inv = NULL;
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Cell* overflow_cell = NULL;
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for(auto c : muxsel_conns)
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{
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if(c->type != ID($logic_not))
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if(extract.count_is_up && c->type != ID($eq))
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continue;
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if(!extract.count_is_up && c->type != ID($logic_not))
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continue;
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if(!is_full_bus(muxsel, index, c, ID::Y, count_mux, ID(S), true))
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continue;
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underflow_inv = c;
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overflow_cell = c;
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break;
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}
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if(underflow_inv == NULL)
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if(overflow_cell == NULL)
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return 13;
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extract.underflow_inv = underflow_inv;
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extract.overflow_cell = overflow_cell;
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//Y connection of the mux must have exactly one load, the counter's internal register, if there's no clock enable
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//If we have a clock enable, Y drives the B input of a mux. A of that mux must come from our register
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@ -309,7 +409,7 @@ int counter_tryextract(
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{
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for(auto c : cnout_loads)
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{
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if(c == underflow_inv)
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if(c == overflow_cell)
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continue;
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if(c == cell)
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continue;
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@ -348,21 +448,62 @@ int counter_tryextract(
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extract.has_pout = true;
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}
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}
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if(!is_full_bus(cnout, index, count_reg, ID(Q), underflow_inv, ID::A, true))
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return 18;
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if(!is_full_bus(cnout, index, count_reg, ID(Q), cell, ID::A, true))
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if(!extract.count_is_up)
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{
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if(!is_full_bus(cnout, index, count_reg, ID(Q), overflow_cell, ID::A, true))
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return 18;
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}
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else
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{
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if(is_full_bus(cnout, index, count_reg, ID(Q), overflow_cell, ID::A, true))
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{
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// B must be the overflow value
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const RTLIL::SigSpec overflow = sigmap(overflow_cell->getPort(ID::B));
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if(!overflow.is_fully_const())
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return 12;
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extract.count_value = overflow.as_int();
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}
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else if(is_full_bus(cnout, index, count_reg, ID(Q), overflow_cell, ID::B, true))
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{
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// A must be the overflow value
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const RTLIL::SigSpec overflow = sigmap(overflow_cell->getPort(ID::A));
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if(!overflow.is_fully_const())
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return 12;
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extract.count_value = overflow.as_int();
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}
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else
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{
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return 18;
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}
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}
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if(alu_port_use_a && !is_full_bus(cnout, index, count_reg, ID(Q), cell, ID::A, true))
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return 19;
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if(!alu_port_use_a && !is_full_bus(cnout, index, count_reg, ID(Q), cell, ID::B, true))
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return 19;
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//Look up the clock from the register
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extract.clk = sigmap(count_reg->getPort(ID(CLK)));
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//Register output net must have an INIT attribute equal to the count value
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extract.rwire = cnout.as_wire();
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if(extract.rwire->attributes.find(ID(init)) == extract.rwire->attributes.end())
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return 20;
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int rinit = extract.rwire->attributes[ID(init)].as_int();
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if(rinit != extract.count_value)
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return 21;
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if(!extract.count_is_up)
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{
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//Register output net must have an INIT attribute equal to the count value
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extract.rwire = cnout.as_wire();
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if(extract.rwire->attributes.find(ID(init)) == extract.rwire->attributes.end())
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return 20;
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int rinit = extract.rwire->attributes[ID(init)].as_int();
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if(rinit != extract.count_value)
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return 21;
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}
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else
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{
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//Register output net must not have an INIT attribute or it must be zero
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extract.rwire = cnout.as_wire();
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if(extract.rwire->attributes.find(ID(init)) == extract.rwire->attributes.end())
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return 0;
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int rinit = extract.rwire->attributes[ID(init)].as_int();
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if(rinit != 0)
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return 21;
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}
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return 0;
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}
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@ -385,20 +526,24 @@ void counter_worker(
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//If it's not a wire, don't even try
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auto port = sigmap(cell->getPort(ID::A));
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if(!port.is_wire())
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return;
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RTLIL::Wire* a_wire = port.as_wire();
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{
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port = sigmap(cell->getPort(ID::B));
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if(!port.is_wire())
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return;
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}
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RTLIL::Wire* port_wire = port.as_wire();
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bool force_extract = false;
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bool never_extract = false;
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string count_reg_src = a_wire->attributes[ID(src)].decode_string().c_str();
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if(a_wire->attributes.find(ID(COUNT_EXTRACT)) != a_wire->attributes.end())
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string count_reg_src = port_wire->attributes[ID(src)].decode_string().c_str();
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if(port_wire->attributes.find(ID(COUNT_EXTRACT)) != port_wire->attributes.end())
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{
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pool<string> sa = a_wire->get_strpool_attribute(ID(COUNT_EXTRACT));
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pool<string> sa = port_wire->get_strpool_attribute(ID(COUNT_EXTRACT));
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string extract_value;
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if(sa.size() >= 1)
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{
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extract_value = *sa.begin();
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log(" Signal %s declared at %s has COUNT_EXTRACT = %s\n",
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log_id(a_wire),
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log_id(port_wire),
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count_reg_src.c_str(),
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extract_value.c_str());
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@ -432,9 +577,9 @@ void counter_worker(
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"counter is too large/small", //1
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"counter does not count by one", //2
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"counter uses signed math", //3
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"counter does not count by one", //4
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"ALU is not a subtractor", //5
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"ALU is not a subtractor", //6
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"RESERVED, not implemented", //4
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"ALU is not an adder/subtractor", //5
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"RESERVED, not implemented", //6
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"ALU ports used outside counter", //7
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"ALU ports used outside counter", //8
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"ALU output used outside counter", //9
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@ -453,14 +598,15 @@ void counter_worker(
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"RESERVED, not implemented", //22, kept for compatibility but not used anymore
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"Reset is not to zero or COUNT_TO", //23
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"Clock enable configuration is unsupported", //24
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"Async reset used but not permitted" //25
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"Async reset used but not permitted", //25
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"Count direction is not allowed" //26
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};
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if(force_extract)
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{
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log_error(
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"Counter extraction is set to FORCE on register %s, but a counter could not be inferred (%s)\n",
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log_id(a_wire),
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log_id(port_wire),
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reasons[reason]);
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}
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return;
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@ -534,11 +680,21 @@ void counter_worker(
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cell->setPort(ID(CE), RTLIL::Const(1));
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}
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//Hook up hard-wired ports (for now up/down are not supported), default to no parallel output
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if(extract.count_is_up)
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{
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cell->setParam(ID(DIRECTION), RTLIL::Const("UP"));
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//XXX: What is this supposed to do?
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cell->setPort(ID(UP), RTLIL::Const(1));
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}
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else
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{
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cell->setParam(ID(DIRECTION), RTLIL::Const("DOWN"));
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cell->setPort(ID(UP), RTLIL::Const(0));
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}
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//Hook up hard-wired ports, default to no parallel output
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cell->setParam(ID(HAS_POUT), RTLIL::Const(0));
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cell->setParam(ID(RESET_TO_MAX), RTLIL::Const(0));
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cell->setParam(ID(DIRECTION), RTLIL::Const("DOWN"));
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cell->setPort(ID(UP), RTLIL::Const(0));
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//Hook up any parallel outputs
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for(auto load : extract.pouts)
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@ -555,7 +711,7 @@ void counter_worker(
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//Delete the cells we've replaced (let opt_clean handle deleting the now-redundant wires)
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cells_to_remove.insert(extract.count_mux);
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cells_to_remove.insert(extract.count_reg);
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cells_to_remove.insert(extract.underflow_inv);
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cells_to_remove.insert(extract.overflow_cell);
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//Log it
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total_counters ++;
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@ -570,10 +726,12 @@ void counter_worker(
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//TODO: support other kind of reset
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reset_type += " async resettable";
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}
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log(" Found %d-bit (%s) down counter %s (counting from %d) for register %s, declared at %s\n",
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log(" Found %d-bit (%s) %s counter %s (counting %s %d) for register %s, declared at %s\n",
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extract.width,
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reset_type.c_str(),
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extract.count_is_up ? "up" : "down",
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countname.c_str(),
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extract.count_is_up ? "to" : "from",
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extract.count_value,
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log_id(extract.rwire->name),
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count_reg_src.c_str());
|
||||
|
|
@ -621,6 +779,9 @@ struct ExtractCounterPass : public Pass {
|
|||
log(" -allow_arst yes|no\n");
|
||||
log(" Allow counters to have async reset (default yes)\n");
|
||||
log("\n");
|
||||
log(" -dir up|down|both\n");
|
||||
log(" Look for up-counters, down-counters, or both (default down)\n");
|
||||
log("\n");
|
||||
log(" -pout X,Y,...\n");
|
||||
log(" Only allow parallel output from the counter to the listed cell types\n");
|
||||
log(" (if not specified, parallel outputs are not restricted)\n");
|
||||
|
|
@ -638,6 +799,7 @@ struct ExtractCounterPass : public Pass {
|
|||
.maxwidth = 64,
|
||||
.minwidth = 2,
|
||||
.allow_arst = true,
|
||||
.allowed_dirs = 0,
|
||||
};
|
||||
|
||||
size_t argidx;
|
||||
|
|
@ -681,7 +843,27 @@ struct ExtractCounterPass : public Pass {
|
|||
|
||||
if (args[argidx] == "-allow_arst" && argidx+1 < args.size())
|
||||
{
|
||||
settings.allow_arst = args[++argidx] == "yes";
|
||||
auto arg = args[++argidx];
|
||||
if (arg == "yes")
|
||||
settings.allow_arst = true;
|
||||
else if (arg == "no")
|
||||
settings.allow_arst = false;
|
||||
else
|
||||
log_error("Invalid -allow_arst value \"%s\"\n", arg.c_str());
|
||||
continue;
|
||||
}
|
||||
|
||||
if (args[argidx] == "-dir" && argidx+1 < args.size())
|
||||
{
|
||||
auto arg = args[++argidx];
|
||||
if (arg == "up")
|
||||
settings.allowed_dirs = 1;
|
||||
else if (arg == "down")
|
||||
settings.allowed_dirs = 0;
|
||||
else if (arg == "both")
|
||||
settings.allowed_dirs = 2;
|
||||
else
|
||||
log_error("Invalid -dir value \"%s\"\n", arg.c_str());
|
||||
continue;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue