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14040 Commits

Author SHA1 Message Date
Krystine Sherwin 2b10bd5070
docs: update images makefile 
Correct path to 011 source.
Also path for resources target.
Set timezone to 'Z' for faketime.

Not sure how to avoid needing to `make resources` before `make all` (or running
`make all` twice) in order to properly generate the presentation images.
 2023-11-01 10:48:04 +13:00
Krystine Sherwin 8e07030fee
docs: update auxiliary programs 
Now includes usage output, (hopefully) generated by the tool during the docs build process so it will always be up to date.
Included in makefile as `docs/usage` target.
Also some updates/additions to the description text, esp `yosys-filterlib` and `yosys-smtbmc`.
 2023-11-01 10:15:58 +13:00
N. Engelhardt f9ab6e147a mem: only import attributes from ports if the memory doesn't have them yet 2023-10-30 16:31:53 +01:00
Krystine Sherwin 74c1fc1cdd
docs: Reference chapters with doc tag 
Fix some formatting.
 2023-10-30 22:38:47 +13:00
Krystine Sherwin d4e45cdccb
docs: Stub new(er) auxlibs and auxprogs 
Still need to actually be filled in.
Also rearranges auxlibs to be alphabetical order.
 2023-10-30 11:21:31 +13:00
Krystine Sherwin e49903f8b1
List all synth commands on synth page 2023-10-30 11:04:03 +13:00
Krystine Sherwin a1c3755dd6
Fix typo 2023-10-30 10:35:23 +13:00
Krystine Sherwin abd92225a3
Replace 010 and 012 with pdf 
Comment out the body text and instead include just the abstract and a download link.
Also orphan the pages so they aren't accessible except by direct link, or via search.
 2023-10-30 10:34:30 +13:00
github-actions[bot] 672375ed02 Bump version 2023-10-26 00:14:46 +00:00
Catherine 6ffc315936 cxxrtl: export wire attributes through the C API. 
Co-authored-by: Charlotte <charlotte@lottia.net>
 2023-10-25 16:01:48 +00:00
N. Engelhardt 080da693d1 memory_libmap: update search order for attributes 2023-10-24 13:55:45 +02:00
N. Engelhardt 833b67af80 verific: import attributes on ports 
Co-authored-by: Miodrag Milanović <mmicko@gmail.com>
 2023-10-20 18:31:41 +02:00
N. Engelhardt 1b6d1e9419 memory_libmap: look for ram_style attributes on surrounding signals 2023-10-19 19:23:35 +02:00
Lofty d21c464ae4
Merge pull request #3946 from rmlarsen/toposort 
Speed up TopoSort by 2.7-3.3x.
 2023-10-17 13:00:18 +01:00
Lofty 5f78d1d03e
Merge pull request #4003 from povik/pp3-test-fix 
quicklogic: Fix pp3 `dffs` test
 2023-10-17 12:25:09 +01:00
github-actions[bot] a5c04dd72e Bump version 2023-10-17 00:15:28 +00:00
Claire Xen a4951a3a97
Merge pull request #3986 from povik/sim-ui-fixes 
Slightly improve `sim` UI
 2023-10-16 16:54:05 +02:00
N. Engelhardt a2f59cf911
Merge pull request #3990 from zeldin/deterministic_scc 2023-10-16 16:51:54 +02:00
N. Engelhardt edee11bcc1
Merge pull request #3873 from povik/peepopt-work 2023-10-16 16:24:09 +02:00
Martin Povišer d6d1cc705e pmgen: Fix sample syntax 2023-10-16 14:19:15 +02:00
Martin Povišer 660be4a31e peepopt: Describe rules in help message 2023-10-16 14:19:15 +02:00
Martin Povišer 5c0c8251c3 peepopt: Remove broken `-generate` option 2023-10-16 14:19:10 +02:00
Martin Povišer aa9b86aeec peepopt: Add left-shift 'shiftmul' variant 
Add a separate shiftmul pattern to match on left shifts which implement
demuxing. This mirrors the right shift pattern matcher but is probably
best kept separate instead of merging the two into a single matcher.
In any case the diff of the two matchers should be easily readable.
 2023-10-16 13:52:38 +02:00
Martin Povišer 038a5e1ed4 peepopt: Support shift amounts zero-padded from below 
The `opt_expr` pass running before `peepopt` can interfere with the
detection of a shiftmul pattern due to some of the bottom bits of the
shift amount being replaced with constant zero. Extend the detection to
cover those situations as well.
 2023-10-16 13:52:06 +02:00
Martin Povišer dd1a8ae49a peepopt: Try to use original wires 2023-10-16 13:52:06 +02:00
Martin Povišer bd8a81a907 peepopt: Clean up 'shiftmul' a bit 
No functional change intended.
 2023-10-16 13:52:06 +02:00
Martin Povišer a0c3be3aae peepopt: Drop unused 'initbits' code 
Drop code that was once used by the 'dffmux' pattern but now is unused
after that pattern has been obsoleted by the 'opt_dff' pass.
 2023-10-16 13:52:06 +02:00
Martin Povišer bdd74e61ae celledges: Account for shift down of x-bits wrt B port 2023-10-16 13:29:47 +02:00
Krystine Sherwin 17749ce688
docs: absolute cmd directory 2023-10-16 21:10:03 +13:00
github-actions[bot] 7d30f716e8 Bump version 2023-10-14 00:14:36 +00:00
Miodrag Milanovic 69c252f247 Update abc 2023-10-13 14:32:11 +02:00
Miodrag Milanović c8adb5a2e2
Merge pull request #4001 from YosysHQ/vhdl_arch 
Preserve VHDL architecture name in attribute
 2023-10-13 08:55:26 +02:00
Martin Povišer 62d6338688 quicklogic: Fix pp3 `dffs` test 
Fix name confusion which was making the test look into the vendor's cell
blackbox rather than into the synthesis results.
 2023-10-12 12:45:40 +02:00
N. Engelhardt 6c562c76bc fix handling right shifts 2023-10-12 11:46:09 +02:00
N. Engelhardt 2d6d6a8da1 fix handling a_width != y_width 2023-10-12 11:46:09 +02:00
N. Engelhardt d0e559a34f celledges: support shift ops 2023-10-12 11:46:09 +02:00
Miodrag Milanovic d473a207a1 Preserve VHDL architecture name in attribute 2023-10-12 09:17:06 +02:00
github-actions[bot] 59fbee4009 Bump version 2023-10-12 00:13:29 +00:00
Krystine Sherwin 5a7a7b319a
Fix make clean 2023-10-12 05:02:33 +13:00
Krystine Sherwin ebcbb94a21
Fixing makefile 2023-10-12 04:50:27 +13:00
Miodrag Milanović 417871e831
Merge pull request #3998 from jix/verific-fix-norename 
verific: Use CellBaseName to identify top modules
 2023-10-11 11:10:23 +02:00
Krystine Sherwin 8335044c35
docs: reflowing selections doc 
Combined presentation sections with appnote sections.
Moved a bunch of Yosys one-liners in-line.
Better reference in interactive investigation to memdemo as a part of advanced logic cone selection (esp. because the show commands use some of the advanced features)
 2023-10-11 12:46:26 +13:00
Krystine Sherwin c61ab7d627
docs: Tidying interactive investigation 
More :numref: because I figured out they were only failing if I didn't do a full re-make.
Reflow first section a little to help readability.
Also includes a css change to prevent code block caption text from bunching into the caption number.
 2023-10-11 11:13:06 +13:00
Jannis Harder 4ed708836a verific: Use CellBaseName to identify top modules 2023-10-10 11:51:16 +02:00
Krystine Sherwin 9e35848c8e
docs: initial 011 selections move 
Also deleting the 011 document.
 2023-10-10 12:36:10 +13:00
Krystine Sherwin a019c26b9d
docs: Moving 011 into main body of manual 
Mostly in the `more_scripting` section, with part of the intro in the `scripting_intro`.
Also includes an extra todo on the installation page and some extra notes on where to find `show` details where relevant.
 2023-10-10 12:35:23 +13:00
Krystine Sherwin b0f8059bce
Moving images and static folders 
Images now included relative to the `docs/source` folder instead of the rst file.
Also makes sure to add the updated `yosyshq.css` (which as a sidenote has ended up as `custom.css` in most of the other docs).
 2023-10-10 10:12:50 +13:00
N. Engelhardt 3e22791810
Merge pull request #3975 from rmlarsen/optmerge 2023-10-09 17:05:19 +02:00
github-actions[bot] 11b9deba9f Bump version 2023-10-09 00:15:38 +00:00
Lofty a79b15e947
Merge pull request #3992 from YosysHQ/empty-case-fix 
write_verilog: avoid emitting empty cases.
 2023-10-08 08:05:10 +01:00