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1341 Commits

Author SHA1 Message Date
whitequark ffbd813a8c
Merge pull request #2550 from zachjs/macro-arg-spaces 
verilog: allow spaces in macro arguments
 2021-01-25 10:36:07 +00:00
Zachary Snow 1096b969ef Allow combination of rand and const modifiers 2021-01-21 08:42:05 -07:00
Zachary Snow 006c18fc11 sv: fix support wire and var data type modifiers 2021-01-20 09:16:21 -07:00
Zachary Snow 4fadcc8f25 verilog: allow spaces in macro arguments 2021-01-20 08:49:58 -07:00
whitequark e991ceeef3
Merge pull request #2547 from zachjs/plugin-so-dsym 
Add plugin.so.dSYM to .gitignore
 2021-01-18 20:21:20 +00:00
Zachary Snow 4c108b4419 Add plugin.so.dSYM to .gitignore 
This artifact is automatically generated by the builtin clang on macOS
when -g is used.
 2021-01-18 11:13:21 -07:00
Kamil Rakoczy d69ddf19da Add typedef input/output test 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2021-01-18 17:31:22 +01:00
Marcelina Kościelnicka 01626e6746 opt_share: Fix X and CO signal width for shifted $alu in opt_share. 
These need to be the same length as actual Y, not visible part of Y.

Fixes #2538.
 2021-01-14 14:54:08 +01:00
whitequark bc2de4567c
Merge pull request #2518 from zachjs/recursion 
verilog: improved support for recursive functions
 2021-01-01 09:32:26 +00:00
Zachary Snow 2085d9a55d verilog: improved support for recursive functions 2020-12-31 18:33:59 -07:00
Zachary Snow 75abd90829 sv: complete support for implied task/function port directions 2020-12-31 16:17:13 -07:00
Zachary Snow 750831e3e0 Fix elaboration of whole memory words used as indices 2020-12-26 21:47:38 -07:00
Zachary Snow 1419c8761c Fix constants bound to redeclared function args 
The changes in #2476 ensured that function inputs like `input x;`
retained their single-bit size when instantiated with a constant
argument and turned into a localparam. That change did not handle the
possibility for an input to be redeclared later on with an explicit
width, such as `integer x;`.
 2020-12-26 08:48:01 -07:00
whitequark deff6a9546
Merge pull request #2501 from zachjs/genrtlil-tern-sign 
genrtlil: fix mux2rtlil generated wire signedness
 2020-12-23 23:15:56 +00:00
whitequark 8ef6b77dc3
Merge pull request #2476 from zachjs/const-arg-width 
Fix constants bound to single bit arguments (fixes #2383)
 2020-12-23 23:15:30 +00:00
Zachary Snow 999eec5617 genrtlil: fix mux2rtlil generated wire signedness 2020-12-22 17:49:16 -07:00
Zachary Snow 8206546c45 Fix constants bound to single bit arguments (fixes #2383) 2020-12-22 17:01:03 -07:00
whitequark 3e67ab1ebb
Merge pull request #2479 from zachjs/const-arg-hint 
Allow constant function calls in constant function arguments
 2020-12-22 01:31:25 +00:00
Zachary Snow 0d8e5d965f Sign extend port connections where necessary 
- Signed cell outputs are sign extended when bound to larger wires
- Signed connections are sign extended when bound to larger cell inputs
- Sign extension is performed in hierarchy and flatten phases
- genrtlil indirects signed constants through signed wires
- Other phases producing RTLIL may need to be updated to preserve
  signedness information
- Resolves #1418
- Resolves #2265
 2020-12-18 20:33:14 -07:00
Zachary Snow 186d6df4c3 Allow constant function calls in constant function arguments 2020-12-07 13:53:27 -07:00
Claire Xen cf67e6a397
Merge pull request #2133 from dh73/nodev_head 
Adding latch tests for shift&mask AST dynamic part-select enhancements
 2020-11-25 09:44:23 +01:00
David Shah 9f241c9a42 nexus: DSP inference support 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-20 08:45:55 +00:00
Xiretza 86e0440da9
Update nexus arch tests to new harness 2020-10-29 14:42:07 +01:00
Marcelina Kościelnicka d3b6b7fe98 xilinx: Fix attributes_test.ys 
This test pretty much passes by accident — the `prep` command runs
memory_collect without memory_dff first, which prevents merging read
register into the memory, and thus blocks block RAM inference for a
reason completely unrelated to the attribute.

The attribute setting didn't actually work because it was set on the
containing module instead of the actual memory.
 2020-10-24 23:52:37 +02:00
Marcelina Kościelnicka eb76d35e80 memory_dff: Fix needlessly duplicating enable bits. 
When the register being merged into the EN signal happens to be a $sdff,
the current code creates a new $mux for every bit, even if they happen
to be identical (as is usually the case), preventing proper grouping
further down the flow.  Fix this by adding a simple cache.

Fixes #2409.
 2020-10-22 13:03:42 +02:00
Miodrag Milanović ac0bd2ffc4
Merge pull request #2397 from daveshah1/nexus 
synth_nexus: Initial implementation
 2020-10-19 11:20:56 +02:00
David Shah 4d584d9319 synth_nexus: Initial implementation 
Signed-off-by: David Shah <dave@ds0.me>
 2020-10-15 08:52:15 +01:00
Marcelina Kościelnicka 7670a89e1f opt_clean: Better memory handling. 
Previously, `$memwr` and `$meminit` cells were always preserved (along
with the memory itself).  With this change, they are instead part of the
main cell mark-and-sweep pass: a memory (and its `$meminit` and `$memwr`
cells) is only preserved iff any associated `$memrd` cell needs to be
preserved.
 2020-10-08 18:05:51 +02:00
clairexen 7e2fc2eaeb
Merge pull request #2378 from udif/pr_dollar_high_low 
Added $high(), $low(), $left(), $right()
 2020-10-01 18:17:36 +02:00
clairexen 2412e75495
Merge pull request #2380 from Xiretza/parallel-tests 
Clean up and parallelize testsuite
 2020-10-01 18:12:31 +02:00
David Shah c4bfbecca6 Update .gitignore 
Signed-off-by: David Shah <dave@ds0.me>
 2020-10-01 15:53:14 +01:00
N. Engelhardt dc4a617694 add tests 2020-09-28 18:16:08 +02:00
Xiretza bed14241ef
tests: add gitignores for auto-generated makefiles 2020-09-26 16:28:24 +02:00
Eddie Hung de79978372
xilinx: do not make DSP48E1 a whitebox for ABC9 by default (#2325) 
* xilinx: eliminate SCCs from DSP48E1 model

* xilinx: add SCC test for DSP48E1

* Update techlibs/xilinx/cells_sim.v

* xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1

Have a test that checks it works through ABC9 when enabled
 2020-09-23 09:15:24 -07:00
N. Engelhardt 370243426e switch argument order to work with macOS getopt 2020-09-23 12:48:26 +02:00
Xiretza e38b830cbb
tests/simple: remove "nullglob" shopt 2020-09-21 15:07:02 +02:00
Xiretza 01260344d3
tests: Parallelize 2020-09-21 15:07:02 +02:00
Xiretza acd47bbd52
tests: Centralize test collection and Makefile generation 2020-09-21 15:07:02 +02:00
clairexen f176bd7778
Merge pull request #2329 from antmicro/arrays-fix-multirange-size 
Rewrite multirange arrays sizes [n] as [n-1:0]
 2020-09-17 18:27:05 +02:00
clairexen 9e937961dc
Merge pull request #2330 from antmicro/arrays-fix-multirange-access 
Fix unsupported subarray access detection
 2020-09-17 18:21:53 +02:00
Udi Finkelstein 7ed0e23e19 We can now handle array slices (e.g. $size(x[1]) etc. ) 2020-09-17 00:55:17 +03:00
Udi Finkelstein b548722bee Added $high(), $low(), $left(), $right() 2020-09-15 20:49:52 +03:00
Miodrag Milanović da3002e580
Merge pull request #2369 from Xiretza/gitignores 
Add missing gitignores for test artifacts
 2020-09-10 13:37:49 +02:00
clairexen a10893072b
Merge pull request #2352 from zachjs/const-func-localparam 
Allow localparams in constant functions
 2020-09-01 17:31:48 +02:00
clairexen 3e1840d036
Merge pull request #2353 from zachjs/top-scope 
Module name scope support
 2020-09-01 17:30:09 +02:00
clairexen 452442ac2f
Merge pull request #2365 from zachjs/const-arg-loop-split-type 
Fix constant args used with function ports split across declarations
 2020-09-01 17:28:35 +02:00
Xiretza 6224fd9055
Add missing gitignores for test artifacts 2020-08-31 19:43:51 +02:00
Zachary Snow ecc5c23b4d Fix constant args used with function ports split across declarations 2020-08-29 13:31:02 -04:00
whitequark 2d10d59d93
Merge pull request #2356 from whitequark/flatten-techmap-no-tpl_driven-sigmap 
flatten, techmap: don't canonicalize tpl driven bits via sigmap
 2020-08-27 11:28:31 +00:00
Dan Ravensloft 1a07b330f8 intel_alm: Add multiply signedness to cells 
Quartus assumes unsigned multiplication by default, breaking signed
multiplies, so add an input signedness parameter to the MISTRAL_MUL*
cells to propagate to Quartus' <family>_mac cells.
 2020-08-26 22:50:16 +02:00