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158 Commits

Author SHA1 Message Date
Zachary Snow 0d8e5d965f Sign extend port connections where necessary 
- Signed cell outputs are sign extended when bound to larger wires
- Signed connections are sign extended when bound to larger cell inputs
- Sign extension is performed in hierarchy and flatten phases
- genrtlil indirects signed constants through signed wires
- Other phases producing RTLIL may need to be updated to preserve
  signedness information
- Resolves #1418
- Resolves #2265
 2020-12-18 20:33:14 -07:00
Miodrag Milanovic 412332fdb3 Validate parameters only when they are used 2020-09-25 11:40:37 +02:00
whitequark 00e7dec7f5 Replace "ILANG" with "RTLIL" everywhere. 
The only difference between "RTLIL" and "ILANG" is that the latter is
the text representation of the former, as opposed to the in-memory
graph representation. This distinction serves no purpose but confuses
people: it is not obvious that the ILANG backend writes RTLIL graphs.

Passes `write_ilang` and `read_ilang` are provided as aliases to
`write_rtlil` and `read_rtlil` for compatibility.
 2020-08-26 17:29:32 +00:00
whitequark 7191dd16f9 Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
clairexen 0f209378a8
Merge pull request #2089 from rswarbrick/modports 
Simplify a modport check in hierarchy.cc
 2020-06-08 15:48:11 +02:00
Rupert Swarbrick 1158bbf7db Fix small typos in documentation for hierarchy command 2020-05-28 11:39:44 +01:00
Rupert Swarbrick 7746bba69a Simplify a modport check in hierarchy.cc 
This code originally comes from commit 458a940. When an interface is
used via a modport, code in genrtlil.cc sets '\\interface_type' and
'\\interface_modport' properties on the wire.

In hierarchy.cc, we pick up the modport name and add it to a dict
called modports_used_in_submodule (that maps connection source to
modport name).

Before this patch, the modport name is retrieved as a strpool and then
iterated over in an arbitrary order, discarding all entries but the
last. In practice, the pool will always have 0 or 1 entries because
the string used to construct it is a valid identifier, so doesn't
contain any pipe symbols.

This patch changes the code to retrieve the modport name as just a
string. This will have the same effect in practice, but may be a bit
less confusing!

The code also gets moved down closer to where the result is used,
which might be a bit more efficient since we won't always get as far
as the check.

The patch also removes some commented-out code, which I think was
intended to add some typechecking at some point, but was never
implemented. Since this dates back to October 2018, I think it makes
more sense to just take it out.
 2020-05-26 16:50:42 +01:00
Marcelina Kościelnicka 846c79b312 hierarchy: Convert positional parameters to named. 
Fixes #1821.
 2020-04-21 19:09:00 +02:00
Alberto Gonzalez d6de14a0d6
Use more descriptive variable name. 
Co-Authored-By: whitequark <whitequark@whitequark.org>
 2020-04-06 14:37:07 +00:00
Alberto Gonzalez 5431ce694c
Clean up `passes/hierarchy/submod.cc`. 2020-04-05 04:39:54 +00:00
Eddie Hung 956ecd48f7 kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
Eddie Hung fdafb74eb7 kernel: use more ID::* 2020-04-02 07:14:08 -07:00
Alberto Gonzalez 4c92f9380c
Fix double deletion in `passes/hierarchy/hierarchy.cc`. 
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
 2020-03-30 16:43:54 +00:00
Alberto Gonzalez b88faceced
Clean up pseudo-private member usage in `passes/hierarchy/hierarchy.cc`. 2020-03-19 06:49:52 +00:00
Claire Wolf 879124333f
Merge pull request #1519 from YosysHQ/eddie/submod_po 
submod: several bugfixes
 2020-03-03 08:19:06 -08:00
David Shah 4bfd2ef4f3 sv: Improve handling of wildcard port connections 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-02 16:12:33 +00:00
David Shah 7e741714df hierarchy: Correct handling of wildcard port connections with default values 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-02 16:12:33 +00:00
David Shah 5df591c023 hierarchy: Resolve SV wildcard port connections 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-02 16:12:33 +00:00
Eddie Hung a265a84632 Use pool instead of std::set for determinism 2019-12-02 01:28:28 -08:00
Eddie Hung b3a66dff7c Move \init signal for non-port signals as long as internally driven 2019-11-28 12:57:36 -08:00
Eddie Hung 130d3b9639 Fix multiple driver issue 2019-11-27 13:23:31 -08:00
Eddie Hung 1c0ee4f786 Do not replace constants with same wire 2019-11-27 08:18:41 -08:00
Eddie Hung c7aa2c6b79 Cleanup 2019-11-27 01:01:24 -08:00
Eddie Hung cb05fe0f70 Check for nullptr 2019-11-27 00:51:39 -08:00
Eddie Hung d960feeeb0 Stray log_dump 2019-11-27 00:50:25 -08:00
Eddie Hung 8c813632b6 Revert "submod to bitty rather bussy, for bussy wires used as input and output" 
This reverts commit cba3073026.
 2019-11-27 00:48:22 -08:00
Eddie Hung 969f511415 Promote output wires in sigmap so that can be detected 2019-11-26 23:39:14 -08:00
Eddie Hung 5e487b103c Fix submod -hidden 2019-11-26 23:26:25 -08:00
Eddie Hung 435d33c373 Add -hidden option to submod 2019-11-26 23:26:12 -08:00
Eddie Hung eb666b4677 Update docs with bullet points 2019-11-26 11:12:58 -08:00
Eddie Hung 0d7ba77426 Move \init from source wire to submod if output port 2019-11-25 16:07:47 -08:00
Eddie Hung cba3073026 submod to bitty rather bussy, for bussy wires used as input and output 2019-11-22 20:53:58 -08:00
Eddie Hung 8119383f81 Constant driven signals are also an input to submodules 2019-11-22 17:23:51 -08:00
Eddie Hung 573396851a Oops 2019-11-22 17:03:30 -08:00
Eddie Hung 6a52897aee sigmap(wire) should inherit port_output status of POs 2019-11-22 16:48:11 -08:00
Eddie Hung d2306d7b1d Adopt @cliffordwolf's suggestion 2019-09-03 12:18:50 -07:00
Eddie Hung 116c249601 -auto-top should check $abstract (deferred) modules with (* top *) 2019-08-28 19:59:25 -07:00
Eddie Hung 48d0f99406 stoi -> atoi 2019-08-07 11:09:17 -07:00
Eddie Hung ee7c970367 IdString::str().substr() -> IdString::substr() 2019-08-06 19:08:33 -07:00
Eddie Hung 234fcf1724 Fix typos 2019-08-06 19:07:45 -07:00
Eddie Hung e38f40af5b Use IdString::begins_with() 2019-08-06 16:42:25 -07:00
Clifford Wolf 3da5288ce0 Use input default values in hierarchy pass 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-19 11:49:20 +02:00
Clifford Wolf ba2185ead8 Refactor hierarchy wand/wor handling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-28 16:43:25 +02:00
Stefan Biereigel ed625a3102 move wand/wor resolution into hierarchy pass 2019-05-27 18:00:22 +02:00
Clifford Wolf ec39cfd0ad Add "hierarchy -chparam" support for non-verific top modules 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-03 22:03:43 +02:00
Eddie Hung eb21bf3651 log_warning_noprefix -> log_warning as per review 2019-05-03 20:53:25 +02:00
Eddie Hung a27b42e975 WIP -chparam support for hierarchy when verific 2019-05-03 20:53:25 +02:00
Clifford Wolf f4abc21d8a Add "whitebox" attribute, add "read_verilog -wb" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-18 17:45:47 +02:00
Clifford Wolf d0b9b1bece Add "hdlname" attribute 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-26 14:52:48 +01:00
Clifford Wolf ae9286386d Only run derive on blackbox modules when ports have dynamic size 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-02 12:36:46 -08:00