riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
1,658 Commits 81 Branches 48 Tags 64 MiB
Commit Graph

399 Commits

Author SHA1 Message Date
Clifford Wolf c3e779a65f Added $_BUF_ cell type 2014-10-03 10:12:28 +02:00
Clifford Wolf 0b8cfbc6fd Added support for "keep" on modules 2014-09-29 12:51:54 +02:00
Clifford Wolf f9a307a50b namespace Yosys 2014-09-27 16:17:53 +02:00
Clifford Wolf edf11c635a Assert on new logic loops in "share" pass 2014-09-21 12:57:33 +02:00
Clifford Wolf 00964f2f61 Initialize RTLIL::Const from std::vector<bool> 2014-09-19 15:50:55 +02:00
Clifford Wolf fa96cf4a16 Added new CodingReadme file (replaces CodingStyle and CHECKLISTS) 2014-09-16 11:26:44 +02:00
Clifford Wolf b470c480e9 Added the obvious optimizations to alumacc $macc generator 2014-09-15 12:22:03 +02:00
Clifford Wolf 2442eb3832 Fixed monitor notifications for removed cell 2014-09-14 17:04:39 +02:00
Clifford Wolf 7815f81c32 Added "synth" command 2014-09-14 16:09:06 +02:00
Clifford Wolf fcb46138ce Simplified $fa undef model 2014-09-08 16:59:39 +02:00
Clifford Wolf af0c8873bb Added $lcu cell type 2014-09-08 13:31:04 +02:00
Clifford Wolf d46bac3305 Added "$fa" cell type 2014-09-08 12:15:39 +02:00
Clifford Wolf 98e6463ca7 Added $macc eval model 2014-09-06 19:44:28 +02:00
Clifford Wolf fa64942018 Added $macc SAT model 2014-09-06 19:44:11 +02:00
Clifford Wolf b847ec8a0b Added $macc cell type 2014-09-06 15:47:46 +02:00
Ruben Undheim 79cbf9067c Corrected spelling mistakes found by lintian 2014-09-06 08:47:06 +02:00
Clifford Wolf 8927aa6148 Removed $bu0 cell type 2014-09-04 02:07:52 +02:00
Clifford Wolf b9cb483f3e Using $pos models for $bu0 2014-09-03 21:20:59 +02:00
Clifford Wolf 50ac284823 Fixes in $alu SAT- and eval-models 2014-09-03 13:39:46 +02:00
Clifford Wolf da360771a1 Create a default selection stack in RTLIL::Design::Design() 2014-09-02 22:49:24 +02:00
Clifford Wolf c38283dbd0 Small bug fixes in $not, $neg, and $shiftx models 2014-09-02 17:48:41 +02:00
Clifford Wolf 2fcf66b91d Added ConstEval model for $alu cells 2014-09-01 16:35:46 +02:00
Clifford Wolf bae09dca2b Added SAT model for $alu cells 2014-09-01 16:35:25 +02:00
Clifford Wolf e07698818d Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::data 2014-09-01 11:36:02 +02:00
Clifford Wolf 83ec3fa204 Fixed return size of const_*() eval functions 2014-08-31 18:08:26 +02:00
Clifford Wolf be44157c0f Added RTLIL::Const::size() 2014-08-31 18:07:48 +02:00
Clifford Wolf a1c7d4a8e2 Added eval model for $lut cells 2014-08-31 17:43:31 +02:00
Clifford Wolf 0b6769af3f Typo fixes in cell->*Param() API 2014-08-31 17:43:31 +02:00
Clifford Wolf 8649b57b6f Added $lut support in test_cell, techmap, satgen 2014-08-31 17:43:31 +02:00
Clifford Wolf 2a1b08aeb3 Added design->scratchpad 2014-08-30 19:37:12 +02:00
Clifford Wolf 4724d94fbc Added $alu cell type 2014-08-30 18:59:05 +02:00
Clifford Wolf dfbd7dd15a Fixed module->addPmux() 2014-08-30 18:17:22 +02:00
Clifford Wolf eda603105e Added is_signed argument to SigSpec.as_int() and Const.as_int() 2014-08-24 15:14:00 +02:00
Clifford Wolf 58367cd87a Removed compatbility.{h,cc}: Not using open_memstream/fmemopen anymore 2014-08-23 15:14:58 +02:00
Clifford Wolf 19cff41eb4 Changed frontend-api from FILE to std::istream 2014-08-23 15:03:55 +02:00
Clifford Wolf 5dce303a2a Changed backend-api from FILE to std::ostream 2014-08-23 13:54:21 +02:00
Clifford Wolf 98442e019d Added emscripten (emcc) support to build system and some build fixes 2014-08-22 16:20:22 +02:00
Clifford Wolf a3494fa9ed Added "plugin" command 2014-08-22 14:00:11 +02:00
Clifford Wolf b37d70dfd7 Added mod->addGate() methods for new gate types 2014-08-19 14:26:54 +02:00
Clifford Wolf aa7a3ed83f Fixed proc_{self,share}_dirname error handling 2014-08-17 02:25:59 +02:00
Clifford Wolf f3326a6421 Improved sig.remove2() performance 2014-08-17 02:16:56 +02:00
Clifford Wolf 9bacc0b54c Added stackmap<> container 2014-08-17 00:56:47 +02:00
Clifford Wolf 410d043dd8 Renamed toposort.h to utils.h 2014-08-17 00:55:35 +02:00
Clifford Wolf 7f734ecc09 Added module->uniquify() 2014-08-16 23:50:36 +02:00
Clifford Wolf 47c2637a96 Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_ 2014-08-16 18:29:39 +02:00
Clifford Wolf 56a30cf42c Added CellTypes::cell_evaluable() 2014-08-16 16:17:07 +02:00
Clifford Wolf dbdf89c705 Added log_spacer() 2014-08-16 15:34:00 +02:00
Clifford Wolf b64b38eea2 Renamed $lut ports to follow A-Y naming scheme 2014-08-15 14:18:40 +02:00
Clifford Wolf f092b50148 Renamed $_INV_ cell type to $_NOT_ 2014-08-15 14:11:40 +02:00
Clifford Wolf ca87116449 More idstring sort_by_* helpers and fixed tpl ordering in techmap 2014-08-15 02:40:46 +02:00