riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
11,181 Commits 81 Branches 48 Tags 63 MiB
Commit Graph

11181 Commits

Author SHA1 Message Date
Miodrag Milanovic be7be63fec Check if stimulated 2022-01-26 15:51:43 +01:00
Miodrag Milanovic 9a8939f0a4 Read fst and use data to set inputs 2022-01-26 15:50:38 +01:00
Miodrag Milanovic 8a02616465 Add fstdata helper class 2022-01-26 10:23:38 +01:00
Miodrag Milanovic c811a71301 Cleanup of config to support platforms 2022-01-26 09:58:27 +01:00
Miodrag Milanovic ccfc00705a Add ability to write to FST file 2022-01-26 09:26:19 +01:00
Miodrag Milanovic 9e9083bbe9 Add FST library 2022-01-25 09:53:41 +01:00
github-actions[bot] bc027b2cae Bump version 2022-01-20 01:06:01 +00:00
gatecat f699c4ba58 nexus: Fix BB sim model 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-01-19 18:14:24 +00:00
Miodrag Milanovic 36482680d5 Removed dbits 8 since 9 will always be picked 2022-01-19 08:51:25 +01:00
Miodrag Milanović 4525e419f6
Merge pull request #3120 from Icenowy/anlogic-bram 
anlogic: support BRAM mapping
 2022-01-19 08:49:58 +01:00
github-actions[bot] 59382945a9 Bump version 2022-01-18 01:00:53 +00:00
Miodrag Milanović 55924de708
Merge pull request #3162 from YosysHQ/mmicko/windows_guidelines 
Add info about VS build
 2022-01-17 13:20:45 +01:00
Miodrag Milanović 703306c119
Update guidelines/Windows 
Co-authored-by: N. Engelhardt <nakengelhardt@gmail.com>
 2022-01-17 13:11:15 +01:00
N. Engelhardt 891eec2882
Merge pull request #3145 from nakengelhardt/advertise_suite_in_readme 
mention tabby+oss cad suite in readme
 2022-01-17 12:50:53 +01:00
N. Engelhardt 15b4d05805 mention distributions' package manager 2022-01-17 12:49:32 +01:00
Miodrag Milanović 41e215219b
Add info about VS build 2022-01-17 10:07:56 +01:00
github-actions[bot] 61324cf55f Bump version 2022-01-12 00:59:23 +00:00
Miodrag Milanovic b91533d9f2 Forgot one 2022-01-11 09:39:45 +01:00
Miodrag Milanovic 883b4fb7e6 Change url to https 2022-01-11 08:56:33 +01:00
Miodrag Milanovic c428a894c0 Next dev cycle 2022-01-11 08:39:34 +01:00
Miodrag Milanovic 8b1eafc3ad Release version 0.13 2022-01-11 08:35:50 +01:00
Miodrag Milanovic 64972360a8 Update CHANGELOG 2022-01-11 08:21:12 +01:00
github-actions[bot] 0feba821a8 Bump version 2022-01-09 01:01:33 +00:00
Zachary Snow aa35f24290 sv: auto add nosync to certain always_comb local vars 
If a local variable is always assigned before it is used, then adding
nosync prevents latches from being needlessly generated.
 2022-01-07 22:53:22 -07:00
Zachary Snow 828e85068f sv: fix size cast internal expression extension 2022-01-07 21:21:02 -07:00
github-actions[bot] 59a7150344 Bump version 2022-01-05 01:00:24 +00:00
Zachary Snow 66447e8faf logger: fix unmatched expected warnings and errors 
- Prevent unmatched expected error patterns from self-matching
- Prevent infinite recursion on unmatched expected warnings
- Always print the error message for unmatched error patterns
- Add test coverage for all unmatched message types
- Add test coverage for excess matched logs and warnings
 2022-01-04 13:39:34 -07:00
Austin Seipp b022fe61a7 opt_dff: fix sequence point copy paste bug 
Newer GCCs emit the following warning for opt_dff:

    passes/opt/opt_dff.cc:560:17: warning: operation on ‘ff.Yosys::FfData::has_clk’ may be undefined [-Wsequence-point]
      560 |      ff.has_clk = ff.has_ce = ff.has_clk = false;
          |      ~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Which is correct: the order of whether the read or write of has_clk
occurs first is undefined since there is no sequence point between them.

This is almost certainly just a typo/copy paste error and objectively
wrong, so just fix it.

Signed-off-by: Austin Seipp <aseipp@pobox.com>
 2022-01-04 18:18:08 +01:00
N. Engelhardt 6483e691bc mention tabby+oss cad suite in readme 2022-01-04 15:44:37 +01:00
gatecat 493b5e03e7 manual: Fix cell-stmt order 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-01-03 18:17:10 -07:00
github-actions[bot] 361916ad3e Bump version 2022-01-04 00:58:28 +00:00
Zachary Snow e0e4dfb55e fix iverilog compatibility for new case expr tests 2022-01-03 12:11:41 -07:00
Zachary Snow 207af4196b fixup verilog doubleslash test 
- add generated doubleslash.v to .gitignore
- ensure backend verilog can be read again
 2022-01-03 08:17:46 -07:00
Zachary Snow 8c509a5659 sv: fix size cast clipping expression width 2022-01-03 08:17:35 -07:00
Miodrag Milanovic cb17eeaf50 Update manual 2022-01-03 11:57:11 +01:00
github-actions[bot] cfe940a98b Bump version 2021-12-26 01:00:33 +00:00
Catherine ebe396a2ab
Merge pull request #3127 from whitequark/cxxrtl-no-reset-elided 
cxxrtl: don't reset elided wires with \init attribute
 2021-12-25 12:29:44 +00:00
Catherine fc049e84a9 cxxrtl: don't reset elided wires with \init attribute. 2021-12-25 01:06:10 +00:00
github-actions[bot] 7407a7f3ef Bump version 2021-12-22 00:58:25 +00:00
Lofty d015c2b48a intel_alm: disable 256x40 M10K mode 
This BRAM mode uses both address ports, making it effectively single-port.
Since memory_bram can't presently map to single-port memories, remove it.
 2021-12-22 00:42:33 +01:00
github-actions[bot] 229980d663 Bump version 2021-12-21 00:59:45 +00:00
Marcelina Kościelnicka f84c9d8e17 memory_share: Fix SAT-based sharing for wide ports. 
Fixes #3117.
 2021-12-20 18:40:14 +01:00
github-actions[bot] f599c148c5 Bump version 2021-12-19 01:00:40 +00:00
Zachary Snow 7608985d2c fix width detection of array querying function in case and case item expressions 
I also removed the unnecessary shadowing of `width_hint` and `sign_hint`
in the corresponding case in `simplify()`.
 2021-12-17 21:22:08 -07:00
Icenowy Zheng c2b7ad3b28 anlogic: support BRAM mapping 
Anlogic FPGAs all have two kinds of BRAMs, one is 9bit*1K when being
true dual port (or 18bit*512 when simple dual port), the other is
16bit*2K.

Supports mapping of these two kinds of BRAMs. 9Kbit BRAM in SDP mode and
32Kbit BRAM with 8bit width are not support yet.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
 2021-12-17 20:28:22 +08:00
github-actions[bot] 60c3ea367c Bump version 2021-12-17 00:58:02 +00:00
Catherine ed4642e18e
Merge pull request #3115 from whitequark/issue-3112 
cxxrtl: demote wires not inlinable only in debug_eval to locals
 2021-12-16 07:29:29 +00:00
Catherine 73eea51613
Merge pull request #3114 from whitequark/issue-3113 
bugpoint: avoid infinite loop between -connections and -wires
 2021-12-16 07:29:19 +00:00
Thomas Sailer 4cd2f03e36 preprocessor: do not destroy double slash escaped identifiers 
The preprocessor currently destroys double slash containing escaped
identifiers (for example \a//b ). This is due to next_token trying to
convert single line comments (//) into /* */ comments. This then leads
to an unintuitive error message like this:
ERROR: syntax error, unexpected '*'

This patch fixes the error by recognizing escaped identifiers and
returning them as single token. It also adds a testcase.
 2021-12-15 18:06:02 -07:00
Catherine 7f2ea7d222 cxxrtl: demote wires not inlinable only in debug_eval to locals. 
Fixes #3112.

Co-authored-by: Irides <irides@irides.network>
 2021-12-15 09:14:33 +00:00