yosys

Commit Graph

Author	SHA1	Message	Date
Eddie Hung	691686f92c	Tidy up, fix undriven	2019-09-19 20:04:52 -07:00
Eddie Hung	1602516a8b	$__ABC_REG to have WIDTH parameter	2019-09-19 19:37:45 -07:00
Eddie Hung	e09f80479e	Fix DSP48E1 timing by breaking P path if MREG or PREG	2019-09-19 18:59:28 -07:00
Eddie Hung	362a803779	Revert "Different approach to timing" This reverts commit `41256f48a5`.	2019-09-19 18:33:38 -07:00
Eddie Hung	41256f48a5	Different approach to timing	2019-09-19 18:33:29 -07:00
Eddie Hung	5ca25b0c59	Suppress $anyseq warnings	2019-09-19 16:27:14 -07:00
Eddie Hung	595fb611a5	Use (* techmap_autopurge *) to suppress techmap warnings	2019-09-19 15:58:01 -07:00
Eddie Hung	25e0f0c376	Fix copy-paste	2019-09-18 12:19:16 -07:00
Eddie Hung	681be20ca2	Add `undef DSP48E1_INST	2019-09-13 17:07:18 -07:00
Eddie Hung	d0b202c58d	Add no MULT no DPORT config	2019-09-13 12:05:14 -07:00
Eddie Hung	247a63f55d	Add support for MULT and DPORT	2019-09-13 11:45:55 -07:00
Eddie Hung	aaeaab4ac0	Rename to techmap_guard	2019-09-12 17:45:02 -07:00
Eddie Hung	6bb8e6a726	Initial DSP48E1 box support	2019-09-12 17:11:01 -07:00
Eddie Hung	aa1491add3	Resolve TODO with pin assignments for SRL*	2019-09-04 15:47:36 -07:00
Eddie Hung	c26c556384	xilinx to use abc_map.v with -max_iter 1	2019-08-20 19:47:11 -07:00
Eddie Hung	091bf4a18b	Remove sequential extension	2019-08-20 18:16:37 -07:00
Eddie Hung	aa2d3af631	LUTMUX -> LUTMUX6	2019-08-20 18:08:07 -07:00
Eddie Hung	54284aaa98	Remove delays from abc_map.v	2019-08-20 17:52:27 -07:00
Eddie Hung	96f00e9147	Typo	2019-08-20 17:51:50 -07:00
Eddie Hung	e273ed5275	Wrap SRL{16,32} too	2019-08-20 15:09:38 -07:00
Eddie Hung	808f07630f	Wrap LUTRAMs in order to capture comb/seq behaviour	2019-08-20 14:49:11 -07:00
Eddie Hung	be9e4f1b67	Use abc_{map,unmap,model}.v	2019-08-20 12:39:11 -07:00

22 Commits