yosys

Commit Graph

Author	SHA1	Message	Date
Clifford Wolf	1de12e1efc	Improved handling of initialized registers	2013-11-23 16:26:59 +01:00
Clifford Wolf	92035fb38e	Implemented indexed part selects	2013-11-20 13:05:27 +01:00
Clifford Wolf	19dba2561e	Implemented part/bit select on memory read	2013-11-20 10:51:32 +01:00
Clifford Wolf	e340532ce5	Added init= attribute for fpga-style reset values	2013-11-20 01:49:37 +01:00
Clifford Wolf	0dfdbd991a	Fixed parsing of module arguments when one type is used for many args	2013-11-19 20:35:31 +01:00
Clifford Wolf	63060dcd2e	Fixed parsing of "parameter integer"	2013-11-13 15:30:23 +01:00
Clifford Wolf	f050c40519	Various fixes for correct parameter support	2013-11-07 10:02:11 +01:00
Clifford Wolf	23cf23418c	Fixed handling of boolean attributes (frontends)	2013-10-24 11:20:13 +02:00
Clifford Wolf	eae43e2db4	Fixed handling of boolean attributes (kernel)	2013-10-24 10:59:27 +02:00
Clifford Wolf	56432a920f	Added defparam support to Verilog/AST frontend	2013-07-04 14:12:33 +02:00
Clifford Wolf	0c6ffc4c65	More fixes for bugs found using xsthammer	2013-06-13 11:18:45 +02:00
Clifford Wolf	46fbe9d262	Added SAT generator and simple sat_solve command	2013-06-07 13:59:13 +02:00
Clifford Wolf	161565be10	Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)	2013-03-31 11:19:11 +02:00
Clifford Wolf	e45d1c8865	Tiny fixes to verilog parser	2013-03-23 18:54:31 +01:00
Clifford Wolf	4f0c2862a0	Added support for verilog genblock[index].member syntax	2013-02-26 13:18:22 +01:00
Clifford Wolf	6d1502b948	Added support for "always @(*)"	2013-01-16 17:32:11 +01:00
Clifford Wolf	7764d0ba1d	initial import	2013-01-05 11:13:26 +01:00

17 Commits