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10422 Commits

Author SHA1 Message Date
georgerennie c1f6ce8b33 Fix SYNTHESIS always being defined in Verilog frontend 2020-12-01 01:37:19 +00:00
Pepijn de Vos f155826a70 add -noalu and -json option for apicula 2020-11-30 11:43:12 +01:00
Julius Roob 2e23dfd96b Return correct modname when found in cache. 2020-11-26 13:31:22 +01:00
Gabriel Somlo 6a328e7032 fixup over commit 829b5cca to re-enable ABCEXTERNAL support 2020-11-26 06:12:12 -05:00
Gabriel Somlo 150b729b6f Add #include needed to build with gcc-11 
Suggested by Jeff Law <law@redhat.com>
 2020-11-26 06:12:12 -05:00
Yosys Bot 2116c58581 Bump version 2020-11-26 00:10:09 +00:00
whitequark 45725d3bdf
Merge pull request #2452 from whitequark/rtlil-remove-dot-identifiers 
rtlil: remove dotted identifiers
 2020-11-25 21:22:14 +00:00
Robert Baruch 2bb3fc654a Further juggles the wording of "character". 2020-11-25 12:02:35 -08:00
Robert Baruch 5d1bb79895 Clarifies how character encodings work. 2020-11-25 11:57:17 -08:00
Miodrag Milanović 180a8e5a45
Merge pull request #2453 from YosysHQ/mmicko/verilog_assignments 
Generate only simple assignments in verilog backend
 2020-11-25 19:15:11 +01:00
Robert Baruch 1faf0e6dcc Clarifies whitespace and eol. 2020-11-25 10:06:22 -08:00
Robert Baruch 5615c41907 Cleans up doublequotes 2020-11-25 09:58:36 -08:00
Robert Baruch 09f6e9d6b6 Clarifies use of integers, and character set. 2020-11-25 09:53:39 -08:00
Miodrag Milanovic 7b093dca10 Add verilog backend option for simple_lhs 2020-11-25 18:21:41 +01:00
Robert Baruch 39af3e629f Clarifies processes, corrects some attributes 2020-11-25 08:59:25 -08:00
whitequark 015b476e56 rtlil: remove dotted identifiers. 
No one knows where they came from and they never did anything useful.
 2020-11-25 16:47:20 +00:00
Miodrag Milanovic addc493e8d generate only simple assignments in verilog backend 2020-11-25 17:43:28 +01:00
Claire Xen cf67e6a397
Merge pull request #2133 from dh73/nodev_head 
Adding latch tests for shift&mask AST dynamic part-select enhancements
 2020-11-25 09:44:23 +01:00
Robert Baruch be938b3094 Refactors for attributes. 2020-11-24 21:59:53 -08:00
whitequark c6b5b18a30
Merge pull request #2442 from cr1901/sccache 
Makefile: Add disabled-by-default ENABLE_SCCACHE config option.
 2020-11-25 02:48:39 +00:00
whitequark 2a39c785a2
Merge pull request #2450 from nitz/sim-vcd-filename 
Add rewrite_filename for sim -vcd argument.
 2020-11-25 02:48:10 +00:00
William D. Jones 9431033921 Makefile: Update ABCREV to bring in sccache fixes. 2020-11-24 21:32:27 -05:00
Yosys Bot 88c47a380b Bump version 2020-11-25 00:10:05 +00:00
Robert Baruch 278b542273 Cleans up some descriptions and syntax 
Now all rules ending in "-stmt" end in eol.
 2020-11-24 15:27:30 -08:00
Chris Dailey cdc802e4b7
Add rewrite_filename for sim -vcd argument. 2020-11-24 15:17:16 -05:00
whitequark bc085761e6
Merge pull request #2428 from whitequark/check-processes 
check: add support for processes
 2020-11-24 15:04:42 +00:00
Miodrag Milanović 5cf738b66a
Merge pull request #2448 from nitz/tcl-script-documentation-fixes 
Tcl script documentation fixes
 2020-11-24 07:51:56 +01:00
Miodrag Milanović b8d3f13307
Merge pull request #2295 from epfl-vlsc/firrtl_blackbox_generic_parameters 
Add firrtl backend support for generic parameters in blackbox components
 2020-11-24 07:50:17 +01:00
nitz cc0d7244b8
tcl -h message only if YOSYS_ENABLE_TCL defined. 2020-11-23 21:48:44 -05:00
Sahand Kashani 930a6ae7db Formatting fixes 2020-11-23 10:55:09 +01:00
Robert Baruch d3d28e287f Adds missing "end" and eol to module. 2020-11-22 21:08:58 -08:00
Robert Baruch c5a2ae01cd Update to Values #2 2020-11-22 18:50:41 -08:00
Robert Baruch 5159dda826 Update to Values section 2020-11-22 18:48:21 -08:00
Robert Baruch 1034422c58 Adds appendix on RTLIL text format 2020-11-22 12:56:29 -08:00
Yosys Bot 949eb95593 Bump version 2020-11-21 00:10:06 +00:00
Miodrag Milanović de58e774ef
Merge pull request #2443 from YosysHQ/dave/nexus-mult-infer 
nexus: Multiplier inference support
 2020-11-20 10:30:56 +01:00
David Shah 9f241c9a42 nexus: DSP inference support 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-20 08:45:55 +00:00
William D. Jones 296a23f489 Makefile: Add disabled-by-default ENABLE_SCCACHE config option. 2020-11-19 13:23:54 -05:00
Yosys Bot 5b35d953f7 Bump version 2020-11-19 00:10:10 +00:00
Miodrag Milanović c8d809897f
Merge pull request #2441 from YosysHQ/dave/nexus_dsp_sim 
nexus: Add DSP simulation model
 2020-11-18 12:22:05 +01:00
David Shah 923843b3fa nexus: Add DSP simulation model 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-18 10:21:17 +00:00
Miodrag Milanovic aa4d94f7d8 Fix duplicated parameter name typo 2020-11-18 10:03:57 +01:00
Yosys Bot 58e8901fee Bump version 2020-11-17 00:10:06 +00:00
William Woodruff c7cf9415f8
backends/blif: Remove unused vector of strings (#2420) 
* backends/blif: Remove unused vector of strings

For reasons that are unclear to me, this was being used to store every
result of `cstr` before returning them. The vector was never accessed otherwise,
resulting in a huge unnecessary memory sink when emitting to BLIF.

* backends/blif: Remove CSTR macro

* backends/blif: Actually call str()
 2020-11-16 09:31:48 +01:00
Miodrag Milanović 2ee5db0211
Merge pull request #2438 from kbeckmann/gowin_rpll 
synth_gowin: Add rPLL blackbox
 2020-11-16 09:30:54 +01:00
Konrad Beckmann 5b9a975eba synth_gowin: Add rPLL blackbox 2020-11-11 17:06:54 +01:00
Yosys Bot 71ca9a8253 Bump version 2020-11-11 00:10:17 +00:00
Miodrag Milanović 924f1713c2
Merge pull request #2433 from YosysHQ/paths_as_globals 
Expose abc and data paths as globals for pyosys
 2020-11-10 08:05:42 +01:00
Yosys Bot 014c7e26b8 Bump version 2020-11-08 00:10:06 +00:00
whitequark 630be7e11a
Merge pull request #2414 from zeldin/abc-depend-clang-fix 
Prevent CXXFLAGS from leaking to abc Makefile
 2020-11-07 18:48:03 +00:00