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Formatting fixes
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@ -178,11 +178,8 @@ std::string dump_const(const RTLIL::Const &data)
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else
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{
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// If value is larger than 32 bits, then emit a binary representation of
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// the number. We have to do this as firrtl number literals don't support
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// specifying their width, therefore a binary literal is the only way to
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// guarantee the parameter widths match that provided on the RHS of a
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// verilog parameter assignment. There is a caveat to this approach
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// though:
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// the number as integers are not large enough to contain the result.
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// There is a caveat to this approach though:
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//
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// Note that parameter may be defined as having a fixed width as follows:
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//
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@ -194,12 +191,12 @@ std::string dump_const(const RTLIL::Const &data)
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// precision, then yosys considers the value you used as an int and
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// assigns it a width of 32 bits regardless of the type of the parameter.
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//
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// defparam <inst_name> .test_signed = 49; (width = 32, though should be 27 based on definition)
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// defparam <inst_name> .test_unsigned = 40'd35; (width = 40, though should be 27 based on definition)
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// defparam <inst_name> .test_signed_large = 40'd12; (width = 40)
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// defparam <inst_name> .test_signed = 49; (width = 32, though should be 27 based on definition)
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// defparam <inst_name> .test_unsigned = 40'd35; (width = 40, though should be 27 based on definition)
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// defparam <inst_name> .test_signed_large = 40'd12; (width = 40)
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//
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// We therefore may lose the precision of the original verilog literal if
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// it was written without it's bitwidth specifier.
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// it was written without its bitwidth specifier.
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// Emit binary prefix for string.
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res_str += "\"b";
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@ -329,7 +326,7 @@ void emit_extmodule(RTLIL::Cell *cell, RTLIL::Module *mod_instance, std::ostream
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* and emit parameterized extmodules with a unique name for each of them. The
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* name that's given to the extmodule is
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*
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* <blackbox_name>_<instance_name>
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* <blackbox_name>_<instance_name>
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*
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* Beware that it is therefore necessary for users to replace "parameterized"
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* instances in the RTLIL sense with these custom extmodules for the firrtl to
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