Eddie Hung
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a2ae393811
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Use module->add{Not,And}Gate() functions
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2019-02-12 09:21:15 -08:00 |
Eddie Hung
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0124512f28
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Add read_xaiger
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2019-02-11 15:19:17 -08:00 |
Eddie Hung
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04c580fde7
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Do not break for constraints
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2019-02-11 13:28:00 -08:00 |
Eddie Hung
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727ba52504
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No increment line_count for binary ANDs
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2019-02-11 13:24:21 -08:00 |
Eddie Hung
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bb4164481d
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Do not ignore newline after AND in binary AIG
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2019-02-11 11:51:44 -08:00 |
Eddie Hung
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8886fa5506
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addDff -> addDffGate as per @daveshah1
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2019-02-08 13:17:53 -08:00 |
Eddie Hung
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afc3c4b613
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Fix tabulation
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2019-02-08 13:17:02 -08:00 |
Eddie Hung
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aa66d8f12f
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-module_name arg to go before -clk_name
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2019-02-08 12:49:55 -08:00 |
Eddie Hung
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fb8ad440a3
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Allow module name to be determined by argument too
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2019-02-08 12:40:43 -08:00 |
Eddie Hung
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f1befe1b44
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Refactor into AigerReader class
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2019-02-08 12:04:26 -08:00 |
Eddie Hung
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2a8cc36578
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Parse binary AIG files
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2019-02-08 11:45:16 -08:00 |
Eddie Hung
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09d758f0a3
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Refactor to parse_aiger_header()
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2019-02-08 10:54:31 -08:00 |
Eddie Hung
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36c56bf412
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Add comment
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2019-02-08 08:37:44 -08:00 |
Eddie Hung
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5e24251a61
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Handle reset logic in latches
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2019-02-08 08:37:18 -08:00 |
Eddie Hung
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652e414392
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Change literal vars from int to unsigned
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2019-02-08 08:09:30 -08:00 |
Eddie Hung
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fafa972238
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Create clk outside of latch loop
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2019-02-08 08:08:49 -08:00 |
Eddie Hung
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02f603ac1a
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Handle latch symbols too
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2019-02-08 08:05:27 -08:00 |
Eddie Hung
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5a593ff41c
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Remove return after log_error
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2019-02-08 08:04:48 -08:00 |
Eddie Hung
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6dbeda1807
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Add support for symbol tables
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2019-02-08 08:03:40 -08:00 |
Eddie Hung
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791f93181d
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Stub for binary AIGER
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2019-02-08 07:31:04 -08:00 |
Eddie Hung
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40db2f2eb6
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Refactor
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2019-02-06 14:58:47 -08:00 |
Eddie Hung
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cc0b723484
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WIP
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2019-02-06 12:19:48 -08:00 |