Commit Graph

27 Commits

Author SHA1 Message Date
whitequark 7191dd16f9 Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
whitequark 8344846787
Merge pull request #2167 from whitequark/cxxrtl-fix-ndebug
cxxrtl: don't compute vital values in log_assert()
2020-06-18 16:57:51 +00:00
whitequark 3c4e974d7b cxxrtl: don't compute vital values in log_assert().
This breaks NDEBUG builds.

Fixes #2166.
2020-06-17 19:27:47 +00:00
whitequark c4f20f744b
Merge pull request #2163 from jfng/cxxrtl-blackbox-debuginfo
cxxrtl: restrict the debug info of a blackbox to its ports.
2020-06-17 06:07:41 +00:00
Jean-François Nguyen 8d98c3861d cxxrtl: restrict the debug info of a blackbox to its ports. 2020-06-16 15:30:56 +02:00
whitequark 8d70f7abf9 cxxrtl: avoid unused variable warning for transparent $memrd ports. NFC. 2020-06-15 06:00:16 +00:00
whitequark dc6961f3d4
Merge pull request #2145 from whitequark/cxxrtl-splitnets
cxxrtl: handle multipart signals
2020-06-13 04:23:22 +00:00
whitequark b793e4753b cxxrtl: elide $pmux cells.
On Minerva, this improves runtime by around 10%, mostly by ensuring
that the logic driving FFs is packed into edge conditionals.
2020-06-12 02:40:30 +00:00
whitequark d5ecd4a570 cxxrtl: annotate port direction as comments. 2020-06-12 00:35:18 +00:00
whitequark 29bd81d662 cxxrtl: unbuffer output wires of toplevel module.
Without unbuffering output wires of, at least, toplevel modules, it
is not possible to have most designs that rely on IO via toplevel
ports (as opposed to using exclusively blackboxes) converge within
one delta cycle. That seriously impairs the performance of CXXRTL.

This commit avoids unbuffering outputs of all modules solely so that
in future, CXXRTL could gain fully separate compilation, and not for
any present technical reason.
2020-06-12 00:31:57 +00:00
whitequark cd7bf115b6 cxxrtl: simplify unbuffering of input wires.
This also fixes an edge case with (*keep*) input ports.
2020-06-12 00:31:57 +00:00
whitequark 8d712b1095 cxxrtl: handle multipart signals.
This avoids losing design visibility when using the `splitnets` pass.
2020-06-11 19:34:35 +00:00
whitequark fa04b19670 cxxrtl: expose RTLIL::{Wire,Memory}->start_offset in debug info. 2020-06-11 12:43:17 +00:00
whitequark 8a4841d786
Merge pull request #2141 from whitequark/cxxrtl-cxx11
cxxrtl: various compiler compatibility fixes
2020-06-10 17:10:15 +00:00
whitequark 6021ff727d cxxrtl: restore C++11 compatibility.
This is necessary to be able to build CXXRTL models via yosys-config.
2020-06-10 15:57:07 +00:00
whitequark 0955a603c8 cxxrtl: disambiguate values/wires and their aliases in debug info.
With this change, it is easier to see which signals carry state (only
wire<>s appear as `reg` in VCD files) and to construct a minimal
checkpoint (CXXRTL_WIRE debug items represent the canonical smallest
set of state required to fully reconstruct the simulation).
2020-06-10 14:39:45 +00:00
whitequark 5467fe563a cxxrtl: allow unbuffering without localizing.
Although logically two separate steps, these were treated as one for
historic reasons. Splitting the two makes it possible to have designs
that are only 2× slower than fastest possible (and are without extra
delta cycles) that allow probing all public wires.
2020-06-09 21:50:09 +00:00
whitequark 970ec34e70 cxxrtl: order -On levels as localize, elide instead of the reverse.
Historically, elision was implemented before localization, so levels
with elision are lower than corresponding levels with localization.
This is unfortunate for two reasons:
  1. Elision is a logical subset of localization, since it equals to
     not giving a name to a temporary.
  2. "Localize" currently actually means "unbuffer and localize",
     and it would be useful to split those steps (at least for
     public wires) for improved design visibility.
2020-06-09 20:55:40 +00:00
whitequark ba11060e59 cxxrtl: factor out -noproc/-noflatten from -O.
Although these options can be thought of as optimizations, they are
essentially orthogonal to the core of -O, which is managing signal
buffering and scope. Going from -O4 to -O2 means going from limited
to complete design visibility, yet in both cases proc and flatten
are desirable.
2020-06-09 20:18:07 +00:00
whitequark bbfe55a8d0 cxxrtl: fix two buggy split_by functions. 2020-06-09 11:05:35 +00:00
whitequark ef4e159447 cxxrtl: ignore cell input signedness when it is irrelevant.
Before this commit, Verilog expressions like `x && 1` would result in
references to `logic_and_us` in generated CXXRTL code, which would
not compile. After this commit, since cells like that actually behave
the same regardless of signedness attributes, the signedness is
ignored, which also reduces the template instantiation pressure.
2020-06-09 07:26:13 +00:00
whitequark 53688a24b5 cxxrtl: fix format of hdlnames.
The CXXRTL code that handled the `hdlname` attribute implemented
outdated semantics.
2020-06-08 20:19:41 +00:00
whitequark f2d7a18756 cxxrtl: emit debug information for constant wires.
Constant wires can represent a significant chunk of the design in
generic designs or after optimization. Emitting them in VCD files
significantly improves usability because gtkwave removes all traces
that are not present in the VCD file after reload, and iterative
development suffers if switching a varying signal to a constant
disrupts the workflow.
2020-06-08 17:29:08 +00:00
whitequark 9b39c6f744 cxxrtl: emit debug information for alias wires.
Alias wires can represent a significant chunk of the design in highly
hierarchical designs; in Minerva SRAM, there are 273 member wires and
527 alias wires. Showing them in every hierarchy level significantly
improves usability.
2020-06-08 17:09:49 +00:00
whitequark 8262997c4e cxxrtl: fix typo in comment. NFC. 2020-06-08 12:50:35 +00:00
whitequark fb3704c896 cxxrtl: minor debug-related improvements. 2020-06-08 12:50:35 +00:00
whitequark ff5500f11a cxxrtl: rename cxxrtl.cc→cxxrtl_backend.cc.
To avoid confusion with the C++ source files that are a part of
the simulation itself and not a part of Yosys build.
2020-06-07 03:48:40 +00:00