yosys

Commit Graph

Author	SHA1	Message	Date
Clifford Wolf	fc3b3c4ec3	Added $slice and $concat cell types	2014-02-07 17:44:57 +01:00
Clifford Wolf	369bf81a70	Added support for non-const === and !== (for miter circuits)	2013-12-27 14:20:15 +01:00
Clifford Wolf	f4b46ed31e	Replaced signed_parameters API with CONST_FLAG_SIGNED	2013-12-04 14:24:44 +01:00
Clifford Wolf	93a70959f3	Replaced RTLIL::Const::str with generic decoder method	2013-12-04 14:14:05 +01:00
Clifford Wolf	41205afc39	Added proper dumping of signed/unsigned parameters to verilog backend	2013-11-24 17:47:22 +01:00
Clifford Wolf	295e352ba6	Renamed "placeholder" to "blackbox"	2013-11-22 15:01:12 +01:00
Clifford Wolf	40d9542647	Implemented $_DFFSR_ expression generator in verilog backend	2013-11-21 21:52:30 +01:00
Clifford Wolf	1dcb683fcb	Write yosys version to output files	2013-11-03 21:41:39 +01:00
Clifford Wolf	e9dede01ca	Fixed handling of boolean attributes (backends)	2013-10-24 11:27:30 +02:00
Clifford Wolf	eae43e2db4	Fixed handling of boolean attributes (kernel)	2013-10-24 10:59:27 +02:00
Clifford Wolf	e0f693cbb0	Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_	2013-10-18 12:13:34 +02:00
Clifford Wolf	5998c101a4	Added $sr, $dffsr and $dlatch cell types	2013-10-18 11:56:16 +02:00
Clifford Wolf	73914d1a41	Added -selected option to various backends	2013-09-03 19:10:11 +02:00
Clifford Wolf	39ee561169	More explicit integer output in verilog backend	2013-08-22 20:31:04 +02:00
Clifford Wolf	7bfc7b61a8	Implemented proper handling of stub placeholder modules	2013-03-28 09:20:10 +01:00
Clifford Wolf	87c7717566	Avoid verilog-2k in verilog backend	2013-03-21 09:51:25 +01:00
Clifford Wolf	11789db206	More support code for $sr cells	2013-03-14 11:15:00 +01:00
Clifford Wolf	441e5fbfca	Fixed a gcc compiler warning [-Wparentheses]	2013-03-03 22:45:06 +01:00
Clifford Wolf	7fccad92f7	Added more help messages	2013-03-01 00:36:19 +01:00
Clifford Wolf	7764d0ba1d	initial import	2013-01-05 11:13:26 +01:00

20 Commits