riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
9,877 Commits 81 Branches 48 Tags 63 MiB
Commit Graph

184 Commits

Author SHA1 Message Date
whitequark fbb346ea91 flatten: preserve original object names via hdlname attribute. 2020-06-08 20:19:41 +00:00
Xiretza 8b0ec3c3a2
Use in-tree include directory in manual build 
This is basically the same issue as in tests/various/plugin.sh,
which uses yosys-config to compile a plugin. `yosys-config --cxxflags`
points to `$PREFIX/share/` (/usr/local/share by default), which might
not exist yet or might be out of date. Building directly from the
headers in ./share/ avoids this.
 2020-05-30 11:21:40 +02:00
clairexen 94c1035389
Merge pull request #1885 from Xiretza/mod-rem-cells 
Fix modulo/remainder semantics
 2020-05-29 16:37:23 +02:00
whitequark efa7424fb9 Restrict RTLIL::IdString to not contain whitespace or control chars. 
This is an existing invariant (most backends can't cope with these)
but one that was not checked or documented.
 2020-05-29 06:43:18 +00:00
Xiretza f88bef7672
Document division and modulo cells 2020-05-28 22:59:04 +02:00
Xiretza edd8ff2c07
Add flooring division operator 
The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $divfloor cell provides this flooring division.

This commit also fixes the handling of $div in opt_expr, which was
previously optimized as if it was $divfloor.
 2020-05-28 22:59:04 +02:00
Xiretza 17163cf43a
Add flooring modulo operator 
The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $modfloor cell provides this flooring modulo (also known as "remainder"
in several languages, but this name is ambiguous).

This commit also fixes the handling of $mod in opt_expr, which was
previously optimized as if it was $modfloor.
 2020-05-28 22:59:03 +02:00
Eddie Hung c34d57de2e Update CHANGELOG and manual for departure from upstream 2020-04-27 12:08:45 -07:00
Marcelina Kościelnicka 38a0c30d65 Get rid of dffsr2dff. 
This pass is a proper subset of opt_rmdff, which is called by opt, which
is called by every synth flow in the coarse part.  Thus, it never
actually does anything and can be safely removed.
 2020-04-15 16:22:37 +02:00
Teguh Hofstee b08932cb81 fix typo in `write_smt2` help 2020-03-23 02:14:26 -07:00
whitequark 161eba253f manual: explain RTLIL::Wire::{upto,offset}. 2020-02-09 14:54:07 +00:00
Claire Wolf 8f40113826
Merge pull request #1553 from whitequark/manual-dffx 
Document $dffe, $dffsr, $_DFFE_*, $_DFFSR_* cells
 2020-01-28 09:41:08 +01:00
Eddie Hung 6d4b6b1e69
Merge pull request #1575 from rodrigomelo9/master 
Fixed some missing "verilog_" in documentation
 2019-12-15 19:00:34 -08:00
Eddie Hung b0231df3e5
Merge pull request #1577 from gromero/for-yosys 
manual: Fix text in Abstract section
 2019-12-15 18:59:55 -08:00
Rodrigo Alejandro Melo e9dc2759c4 Fixed some missing "verilog_" in documentation 2019-12-13 10:17:05 -03:00
Gustavo Romero 993a77d19b manual: Fix text in Abstract section 2019-12-11 08:22:08 -03:00
whitequark 72a5674c03 manual: document $dffe, $dffsr, $_DFFE_*, $_DFFSR_* cells. 2019-12-05 10:28:43 +00:00
whitequark ec4c9267b3 manual: document behavior of many comb cells more precisely. 2019-12-04 11:32:14 +00:00
Clifford Wolf 023086bd46 Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-06 04:47:55 +02:00
whitequark 9251c000e8 manual: explain the purpose of `sync always`. 2019-07-02 17:10:13 +00:00
whitequark addf01d45d Explain exact semantics of switch and case rules in the manual. 2019-06-19 05:22:40 +00:00
Clifford Wolf 71c38d9de5 Add $specrule cells for $setup/$hold/$skew specify rules 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Clifford Wolf aec2475a9d Add CellTypes support for $specify2 and $specify3 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
whitequark fc2dd7ec8e manual: document some gates. 2019-01-14 16:17:25 +00:00
whitequark 7a45122168 manual: explain $tribuf cell. 2019-01-14 16:08:58 +00:00
Clifford Wolf f042559e9d Fix typo in manual 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-07 10:07:28 +01:00
whitequark 182d84ad54 manual: make description of $meminit ports match reality. 2018-12-21 23:04:31 +00:00
whitequark c04908c997 manual: fix typos. 2018-12-20 07:59:40 +00:00
whitequark a9ff81dd82 manual: document $meminit cell and memory_* passes. 2018-12-20 04:54:31 +00:00
Clifford Wolf 500726781b Update command reference manual 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-16 15:28:37 +02:00
acw1251 efac8a45a6 Fixed typo in "verilog_write" help message 2018-09-18 13:34:30 -04:00
Henner Zeller 3aa4484a3c Consistent use of 'override' for virtual methods in derived classes. 
o Not all derived methods were marked 'override', but it is a great
  feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
  provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
  use the plain keyword going forward now that C++11 is established)
 2018-07-20 23:51:06 -07:00
Clifford Wolf eb67a7532b Add $allconst and $allseq cell types 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-02-23 13:14:47 +01:00
Clifford Wolf 05cdd58c8d Add $_ANDNOT_ and $_ORNOT_ gates 2017-05-17 09:08:29 +02:00
Clifford Wolf 5f1d0b1024 Add $live and $fair cell types, add support for s_eventually keyword 2017-02-25 10:36:39 +01:00
Piotr Esden-Tempski e3a12b57f5 Use -E sed parameter instead of -r. 
BSD sed equivalent to -r parameter is -E and it is also supported in GNU
sed thus using -E results in support on both platforms.
 2017-02-04 18:26:01 -08:00
Clifford Wolf 3928482a3c Add $cover cell type and SVA cover() support 2017-02-04 14:14:26 +01:00
Clifford Wolf 4832faf5e9 Updated command reference in manual 2016-11-02 19:25:28 +01:00
Clifford Wolf bdc316db50 Added $anyseq cell type 2016-10-14 15:24:03 +02:00
Clifford Wolf 8ebba8a35f Added $ff and $_FF_ cell types 2016-10-12 01:18:39 +02:00
Clifford Wolf 6f41e5277d Removed $aconst cell type 2016-08-30 19:09:56 +02:00
Clifford Wolf eae390ae17 Removed $predict again 2016-08-28 21:35:33 +02:00
Clifford Wolf 4056312987 Added $anyconst and $aconst 2016-07-27 15:41:22 +02:00
Clifford Wolf 5c166e76e5 Added $initstate cell type and vlog function 2016-07-21 14:23:22 +02:00
Clifford Wolf d7763634b6 After reading the SV spec, using non-standard predict() instead of expect() 2016-07-21 13:34:33 +02:00
Clifford Wolf 721f1f5ecf Added basic support for $expect cells 2016-07-13 16:56:17 +02:00
Clifford Wolf d3f0d72427 Added warning about adding fsm_encoding attributes to wires to manual 2016-07-08 18:31:31 +02:00
Clifford Wolf 52bb1b968d Added $sop cell type and "abc -sop" 2016-06-17 13:50:09 +02:00
Clifford Wolf d05115ceda Minor presentation fixes 2016-05-14 11:35:39 +02:00
Clifford Wolf 0bc95f1e04 Added "yosys -D" feature 2016-04-21 23:28:37 +02:00