Eddie Hung
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875a02a6f2
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abc9 to not select anything extra, and pop selection after final clean
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2019-02-21 14:38:52 -08:00 |
Eddie Hung
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04429f8152
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abc9 to write_xaiger -symbols, not -map
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2019-02-21 14:28:36 -08:00 |
Eddie Hung
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3307295488
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Merge branch 'read_aiger' into xaig
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2019-02-21 14:27:32 -08:00 |
Eddie Hung
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d3ba1f9719
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Merge branch 'read_aiger' of https://github.com/eddiehung/yosys into read_aiger
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2019-02-21 14:17:48 -08:00 |
Eddie Hung
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6ccaf250df
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Merge branch 'read_aiger' into xaig
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2019-02-21 14:14:28 -08:00 |
Eddie Hung
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7f8f36273a
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abc9 to use &mfs
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2019-02-21 13:16:24 -08:00 |
Eddie Hung
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ca870688c3
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Revert "tests/simple to also do LUT synth"
This reverts commit 5994382a20 .
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2019-02-21 13:15:45 -08:00 |
Eddie Hung
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a8803a1519
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Merge remote-tracking branch 'origin/master' into xaig
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2019-02-21 11:23:00 -08:00 |
Eddie Hung
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5994382a20
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tests/simple to also do LUT synth
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2019-02-21 11:16:57 -08:00 |
Eddie Hung
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107da3becf
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Working simple_abc9 tests
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2019-02-21 11:16:25 -08:00 |
Eddie Hung
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6b96df41bc
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abc9 to only disconnect output ports of AND and NOT gates
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2019-02-21 11:15:47 -08:00 |
Eddie Hung
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2f96a0ed32
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write_xaiger to use original bit for co, not sigmap()-ed bit
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2019-02-21 11:15:25 -08:00 |
Eddie Hung
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c6fd057eda
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Add abc9.v testcase to simple_abc9
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2019-02-21 10:37:45 -08:00 |
Clifford Wolf
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d55790909c
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Hotfix for 4c82ddf
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-02-21 19:27:23 +01:00 |
Clifford Wolf
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3b97b612fe
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Merge pull request #822 from litghost/expand_setundef
Add -params mode to force undef parameters in selected cells.
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2019-02-21 19:24:16 +01:00 |
Keith Rothman
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4c82ddf394
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Add -params mode to force undef parameters in selected cells.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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2019-02-21 10:16:38 -08:00 |
Clifford Wolf
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0e371109b0
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Merge pull request #818 from YosysHQ/clifford/dffsrfix
Fix opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_, fixes #816
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2019-02-21 18:58:44 +01:00 |
Clifford Wolf
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03aa3541ae
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Merge pull request #786 from YosysHQ/pmgen
Pattern Matcher Generator and iCE40 DSP Mapper
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2019-02-21 18:56:01 +01:00 |
Clifford Wolf
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893194689d
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Fix typo in passes/pmgen/README.md
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-02-21 18:50:02 +01:00 |
Clifford Wolf
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310b0a0ffa
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Merge pull request #821 from eddiehung/dff_init
Revert "Add -B option to autotest.sh to append to backend_opts"
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2019-02-21 18:46:58 +01:00 |
Eddie Hung
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be061810d7
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Merge branch 'clifford/dffsrfix' of https://github.com/YosysHQ/yosys into xaig
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2019-02-21 09:31:17 -08:00 |
Eddie Hung
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8e789da74c
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Revert "Add -B option to autotest.sh to append to backend_opts"
This reverts commit 281f2aadca .
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2019-02-21 09:22:29 -08:00 |
Clifford Wolf
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2da4c9c8f0
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Fix opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_, fixes #816
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-02-21 13:49:45 +01:00 |
Clifford Wolf
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2fe1c830eb
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Bugfix in ice40_dsp
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-02-21 13:28:46 +01:00 |
Eddie Hung
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7f26043caf
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ABC -> ABC9
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2019-02-20 17:36:57 -08:00 |
Eddie Hung
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e5b8bb9faa
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abc9 to disconnect mapped_mods POs correctly, and do not count $_NOT_
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2019-02-20 17:33:35 -08:00 |
Eddie Hung
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9e299a0908
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read_aiger to not do -purge for clean
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2019-02-20 17:33:04 -08:00 |
Eddie Hung
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31fea5eb33
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Merge pull request #817 from eddiehung/dff_init
Cleanup #805
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2019-02-20 17:26:56 -08:00 |
Eddie Hung
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32853b1f8d
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lut/not/and suffix to be ${lut,not,and}
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2019-02-20 16:30:30 -08:00 |
Eddie Hung
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869343b040
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simple_abc9 tests to now preserve memories
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2019-02-20 16:19:01 -08:00 |
Eddie Hung
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abc1c2672e
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read_aiger to also rename 0 index lut when wideports
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2019-02-20 16:17:22 -08:00 |
Eddie Hung
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01f8d50ba2
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Remove swap file
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2019-02-20 16:17:01 -08:00 |
Eddie Hung
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4035ec8933
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Remove simple_defparam tests
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2019-02-20 15:45:45 -08:00 |
Eddie Hung
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f89b112fbf
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write_aiger: fix CI/CO and symbols
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2019-02-20 15:35:32 -08:00 |
Eddie Hung
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43d5471570
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Move tests/techmap/abc9 to simple_abc9
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2019-02-20 15:34:59 -08:00 |
Eddie Hung
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945bbcc298
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Add tests/simple_abc9
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2019-02-20 15:31:35 -08:00 |
Eddie Hung
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2ca83005fb
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abc9 to cope with multiple modules
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2019-02-20 12:56:15 -08:00 |
Eddie Hung
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d6b317b349
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abc9 to use & syntax for -fast, and name fixes
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2019-02-20 12:40:17 -08:00 |
Eddie Hung
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f9702a8abe
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read_aiger: new naming fixes
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2019-02-20 12:39:51 -08:00 |
Eddie Hung
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83b66861e9
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read_aiger to name wires with internal name, less likely to clash
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2019-02-20 11:22:56 -08:00 |
Eddie Hung
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ef60ca1717
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write_xaiger to not write latches, CO/PO fixes
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2019-02-20 11:09:13 -08:00 |
Eddie Hung
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45ddd9066e
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synth to take -abc9 argument
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2019-02-20 11:08:49 -08:00 |
Clifford Wolf
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84999a7e68
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Add ice40 test_dsp_map test case generator
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-02-20 17:18:59 +01:00 |
Clifford Wolf
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218e9051bb
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Add "synth_ice40 -dsp"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-02-20 16:42:27 +01:00 |
Clifford Wolf
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246391200e
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Add FF support to wreduce
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-02-20 16:36:42 +01:00 |
Clifford Wolf
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7bf4e4a185
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Improve iCE40 SB_MAC16 model
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-02-20 12:55:20 +01:00 |
Clifford Wolf
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dca65d83a0
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Detect and reject cases that do not map well to iCE40 DSPs (yet)
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-02-20 11:18:19 +01:00 |
Eddie Hung
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62e5ff9ba8
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abc9 to cope with indexed wires when creating $lut from $_NOT_
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2019-02-19 16:06:03 -08:00 |
Eddie Hung
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d365682a21
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Add aiger tests to make tests
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2019-02-19 15:25:47 -08:00 |
Eddie Hung
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ef1a1402bc
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Add a quick abc9 test
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2019-02-19 15:25:03 -08:00 |