Commit Graph

4499 Commits

Author SHA1 Message Date
Eddie Hung 875a02a6f2 abc9 to not select anything extra, and pop selection after final clean 2019-02-21 14:38:52 -08:00
Eddie Hung 04429f8152 abc9 to write_xaiger -symbols, not -map 2019-02-21 14:28:36 -08:00
Eddie Hung 3307295488 Merge branch 'read_aiger' into xaig 2019-02-21 14:27:32 -08:00
Eddie Hung d3ba1f9719 Merge branch 'read_aiger' of https://github.com/eddiehung/yosys into read_aiger 2019-02-21 14:17:48 -08:00
Eddie Hung 6ccaf250df Merge branch 'read_aiger' into xaig 2019-02-21 14:14:28 -08:00
Eddie Hung 7f8f36273a abc9 to use &mfs 2019-02-21 13:16:24 -08:00
Eddie Hung ca870688c3 Revert "tests/simple to also do LUT synth"
This reverts commit 5994382a20.
2019-02-21 13:15:45 -08:00
Eddie Hung a8803a1519 Merge remote-tracking branch 'origin/master' into xaig 2019-02-21 11:23:00 -08:00
Eddie Hung 5994382a20 tests/simple to also do LUT synth 2019-02-21 11:16:57 -08:00
Eddie Hung 107da3becf Working simple_abc9 tests 2019-02-21 11:16:25 -08:00
Eddie Hung 6b96df41bc abc9 to only disconnect output ports of AND and NOT gates 2019-02-21 11:15:47 -08:00
Eddie Hung 2f96a0ed32 write_xaiger to use original bit for co, not sigmap()-ed bit 2019-02-21 11:15:25 -08:00
Eddie Hung c6fd057eda Add abc9.v testcase to simple_abc9 2019-02-21 10:37:45 -08:00
Clifford Wolf d55790909c Hotfix for 4c82ddf
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-21 19:27:23 +01:00
Clifford Wolf 3b97b612fe
Merge pull request #822 from litghost/expand_setundef
Add -params mode to force undef parameters in selected cells.
2019-02-21 19:24:16 +01:00
Keith Rothman 4c82ddf394 Add -params mode to force undef parameters in selected cells.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-02-21 10:16:38 -08:00
Clifford Wolf 0e371109b0
Merge pull request #818 from YosysHQ/clifford/dffsrfix
Fix opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_, fixes #816
2019-02-21 18:58:44 +01:00
Clifford Wolf 03aa3541ae
Merge pull request #786 from YosysHQ/pmgen
Pattern Matcher Generator and iCE40 DSP Mapper
2019-02-21 18:56:01 +01:00
Clifford Wolf 893194689d Fix typo in passes/pmgen/README.md
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-21 18:50:02 +01:00
Clifford Wolf 310b0a0ffa
Merge pull request #821 from eddiehung/dff_init
Revert "Add -B option to autotest.sh to append to backend_opts"
2019-02-21 18:46:58 +01:00
Eddie Hung be061810d7 Merge branch 'clifford/dffsrfix' of https://github.com/YosysHQ/yosys into xaig 2019-02-21 09:31:17 -08:00
Eddie Hung 8e789da74c Revert "Add -B option to autotest.sh to append to backend_opts"
This reverts commit 281f2aadca.
2019-02-21 09:22:29 -08:00
Clifford Wolf 2da4c9c8f0 Fix opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_, fixes #816
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-21 13:49:45 +01:00
Clifford Wolf 2fe1c830eb Bugfix in ice40_dsp
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-21 13:28:46 +01:00
Eddie Hung 7f26043caf ABC -> ABC9 2019-02-20 17:36:57 -08:00
Eddie Hung e5b8bb9faa abc9 to disconnect mapped_mods POs correctly, and do not count $_NOT_ 2019-02-20 17:33:35 -08:00
Eddie Hung 9e299a0908 read_aiger to not do -purge for clean 2019-02-20 17:33:04 -08:00
Eddie Hung 31fea5eb33
Merge pull request #817 from eddiehung/dff_init
Cleanup #805
2019-02-20 17:26:56 -08:00
Eddie Hung 32853b1f8d lut/not/and suffix to be ${lut,not,and} 2019-02-20 16:30:30 -08:00
Eddie Hung 869343b040 simple_abc9 tests to now preserve memories 2019-02-20 16:19:01 -08:00
Eddie Hung abc1c2672e read_aiger to also rename 0 index lut when wideports 2019-02-20 16:17:22 -08:00
Eddie Hung 01f8d50ba2 Remove swap file 2019-02-20 16:17:01 -08:00
Eddie Hung 4035ec8933 Remove simple_defparam tests 2019-02-20 15:45:45 -08:00
Eddie Hung f89b112fbf write_aiger: fix CI/CO and symbols 2019-02-20 15:35:32 -08:00
Eddie Hung 43d5471570 Move tests/techmap/abc9 to simple_abc9 2019-02-20 15:34:59 -08:00
Eddie Hung 945bbcc298 Add tests/simple_abc9 2019-02-20 15:31:35 -08:00
Eddie Hung 2ca83005fb abc9 to cope with multiple modules 2019-02-20 12:56:15 -08:00
Eddie Hung d6b317b349 abc9 to use & syntax for -fast, and name fixes 2019-02-20 12:40:17 -08:00
Eddie Hung f9702a8abe read_aiger: new naming fixes 2019-02-20 12:39:51 -08:00
Eddie Hung 83b66861e9 read_aiger to name wires with internal name, less likely to clash 2019-02-20 11:22:56 -08:00
Eddie Hung ef60ca1717 write_xaiger to not write latches, CO/PO fixes 2019-02-20 11:09:13 -08:00
Eddie Hung 45ddd9066e synth to take -abc9 argument 2019-02-20 11:08:49 -08:00
Clifford Wolf 84999a7e68 Add ice40 test_dsp_map test case generator
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-20 17:18:59 +01:00
Clifford Wolf 218e9051bb Add "synth_ice40 -dsp"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-20 16:42:27 +01:00
Clifford Wolf 246391200e Add FF support to wreduce
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-20 16:36:42 +01:00
Clifford Wolf 7bf4e4a185 Improve iCE40 SB_MAC16 model
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-20 12:55:20 +01:00
Clifford Wolf dca65d83a0 Detect and reject cases that do not map well to iCE40 DSPs (yet)
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-20 11:18:19 +01:00
Eddie Hung 62e5ff9ba8 abc9 to cope with indexed wires when creating $lut from $_NOT_ 2019-02-19 16:06:03 -08:00
Eddie Hung d365682a21 Add aiger tests to make tests 2019-02-19 15:25:47 -08:00
Eddie Hung ef1a1402bc Add a quick abc9 test 2019-02-19 15:25:03 -08:00