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7773 Commits

Author SHA1 Message Date
Eddie Hung bfc7164af7 Move LSB-trimming functionality from wreduce to opt_expr 2019-08-06 15:25:50 -07:00
Eddie Hung 84f52aee0d Add SigSpec::extract_end() convenience function 2019-08-06 15:25:11 -07:00
Eddie Hung 0b56be8c56 Restore original SigSpec::extract() 2019-08-06 15:24:55 -07:00
Eddie Hung 51b39219cd Move LSB tests from wreduce to opt_expr 2019-08-06 15:24:49 -07:00
Eddie Hung 26cb3e7afc Merge remote-tracking branch 'origin/master' into eddie/wreduce_add 2019-08-06 14:50:00 -07:00
David Shah 8110fb9266
Merge pull request #1232 from YosysHQ/dave/write_gzip 
Add support for writing gzip-compressed files
 2019-08-06 19:05:35 +01:00
David Shah c43b0c4b49 [wip] DSP48E1 sim model improvements 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-06 18:47:18 +01:00
Clifford Wolf 95a6582f34 Be less aggressive with running design->check() 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-06 19:21:37 +02:00
David Shah 3a3da678ad Add test for writing gzip-compressed files 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-06 17:43:04 +01:00
David Shah 27360ceda6 Add support for writing gzip-compressed files 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-06 17:43:04 +01:00
Clifford Wolf f1f5b4e375 Fix handling of functions/tasks without top-level begin-end block, fixes #1231 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-06 18:06:14 +02:00
Clifford Wolf a4b59de5d4
Merge pull request #1251 from YosysHQ/clifford/nmux 
Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs
 2019-08-06 15:18:18 +02:00
David Shah 7a563d0b92 [wip] DSP48E1 sim model improvements 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-06 13:23:42 +01:00
Clifford Wolf 023086bd46 Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-06 04:47:55 +02:00
Ben Widawsky 7de098ad45 techlibs/intel: Clean up Makefile 
Use GNU make's foreach iterator and remove nonexistent files. Gmake is
already a requirement of the build system.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
 2019-08-05 11:22:11 -07:00
Bogdan Vukobratovic 6a796accc0 Support various binary operators in opt_share 2019-08-04 19:06:38 +02:00
Miodrag Milanovic 8a3329871b clock for ram trough gbuf 2019-08-04 12:17:55 +02:00
Miodrag Milanovic cf96f41c6d Added bram support 2019-08-04 11:46:36 +02:00
Miodrag Milanovic 837cb0a1b9 anlogic : Fix alu mapping 2019-08-03 14:47:33 +02:00
Miodrag Milanovic 6e210f26fa Custom step to add global clock buffers 2019-08-03 14:40:23 +02:00
Miodrag Milanovic ab98f604fd Initial EFINIX support 2019-08-03 13:10:44 +02:00
Bogdan Vukobratovic d8be5ce6ba Tabs to spaces in opt_share examples 2019-08-03 12:35:46 +02:00
Bogdan Vukobratovic 280c4e7794 Fix spacing in opt_share tests, change wording in opt_share help 2019-08-03 12:28:46 +02:00
whitequark 44a9dcbbbf
Merge pull request #1242 from jfng/fix-proc_prune-partial 
proc_prune: Promote partially redundant assignments.
 2019-08-03 07:08:41 +00:00
Miodrag Milanovic 2b4e50ac3d Visual Studio build fix 2019-08-02 17:08:59 +02:00
Clifford Wolf 0917a5cf72
Merge pull request #1238 from mmicko/vsbuild_fix 
Visual Studio build fix
 2019-08-02 17:07:39 +02:00
Miodrag Milanovic 2ec5a3ec92 Fix linking issue for new mxe and pthread 2019-08-02 16:55:14 +02:00
Miodrag Milanovic ce0de937f4 Fix yosys linking for mxe 2019-08-02 16:55:14 +02:00
Miodrag Milanovic bf59f31b43 New mxe hacks needed to support 2ca237e 2019-08-02 16:55:14 +02:00
Miodrag Milanovic e9c5f1b346 Fix formatting for msys2 mingw build using GetSize 2019-08-02 16:55:14 +02:00
Clifford Wolf f4ae6afc22
Merge pull request #1239 from mmicko/mingw_fix 
Fix formatting for msys2 mingw build
 2019-08-02 16:37:57 +02:00
Eddie Hung c39b1a6fcf Add comment about supporting $dffe in ice40_dsp 2019-08-01 15:13:18 -07:00
Eddie Hung ed7540a46f Pack P register properly 2019-08-01 15:10:43 -07:00
Eddie Hung 105aaeaf59 Trim Y_WIDTH 2019-08-01 14:33:16 -07:00
Eddie Hung 65de9aaaa9 Add DSP_SIGNEDONLY back 2019-08-01 14:29:00 -07:00
Eddie Hung 915f4e34bf DSP_MINWIDTH -> DSP_{A,B,Y}_MINWIDTH 2019-08-01 13:20:34 -07:00
Eddie Hung fc0b5d5ab6 Change $__softmul back to $mul 2019-08-01 12:45:14 -07:00
Eddie Hung e19d33b003 Cope with sign extension in mul2dsp 2019-08-01 12:44:56 -07:00
Eddie Hung 332b86491d Revert "Do not do sign extension in techmap; let packer do it" 
This reverts commit 595a8f032f.
 2019-08-01 12:17:14 -07:00
Eddie Hung ed303b07b7 Merge remote-tracking branch 'origin/master' into xc7dsp 2019-08-01 12:02:16 -07:00
Eddie Hung 7e86c8bcfb Fix B_WIDTH > DSP_B_MAXWIDTH case 2019-08-01 10:01:43 -07:00
Eddie Hung c54a39069d CO is sign extension only if signed multiplier 2019-08-01 10:00:49 -07:00
Eddie Hung e3c39cc450 Fix typo 2019-08-01 10:00:01 -07:00
Eddie Hung e8a2d10982
Merge pull request #1236 from YosysHQ/eddie/xc6s_brams_map 
xc6s_brams_map.v: RST -> RSTBRST for RAMB8BWER
 2019-08-01 09:38:55 -07:00
Miodrag Milanovic 7a65ed19a5 Fix linking issue for new mxe and pthread 2019-08-01 17:30:02 +02:00
Miodrag Milanovic 3f633690ae Fix yosys linking for mxe 2019-08-01 17:28:07 +02:00
Miodrag Milanovic f767179c75 New mxe hacks needed to support 2ca237e 2019-08-01 17:28:07 +02:00
Miodrag Milanovic 28b7053a01 Fix formatting for msys2 mingw build using GetSize 2019-08-01 17:27:34 +02:00
Jean-François Nguyen 320bf2fde5 proc_prune: Promote partially redundant assignments. 2019-08-01 13:09:55 +02:00
Clifford Wolf 292f03355a Update JSON front-end to process new attr/param encoding 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-01 12:48:22 +02:00