Eddie Hung
a6d4ea7463
abc9: respect (* keep *) on cells
2020-01-13 19:21:11 -08:00
Eddie Hung
9ec948f396
write_xaiger: add support and test for (* keep *) on wires
2020-01-13 19:07:55 -08:00
Eddie Hung
a10016ccc5
Add abc9 sanity test
2020-01-09 18:17:06 -08:00
Marcin Kościelnicki
a24596def3
iopadmap: Emit tristate buffers with const OE for some edge cases.
2019-12-25 17:37:58 +01:00
Marcin Kościelnicki
2abe38e73e
iopadmap: Refactor and fix tristate buffer mapping. ( #1527 )
...
The previous code for rerouting wires when inserting tristate buffers
was overcomplicated and didn't handle all cases correctly (in
particular, only cell connections were rewired — internal connections
were not).
2019-12-04 08:44:08 +01:00
Marcin Kościelnicki
6cdea425b8
clkbufmap: Add support for inverters in clock path.
2019-11-25 20:40:39 +01:00
Clifford Wolf
0e05424885
Merge pull request #1422 from YosysHQ/eddie/aigmap_select
...
Add -select option to aigmap
2019-10-03 11:54:04 +02:00
Eddie Hung
a4f2f7d23c
Extend test with renaming cells with prefix too
2019-10-02 12:43:18 -07:00
Eddie Hung
369652d4b9
Add test
2019-09-30 17:20:39 -07:00
Eddie Hung
8b239ee707
Add quick test
2019-09-30 15:34:04 -07:00
Marcin Kościelnicki
fd0e3a2c43
Fix _TECHMAP_REMOVEINIT_ handling.
...
Previously, this wire was handled in the code that populated the "do or
do not" techmap cache, resulting in init value removal being performed
only for the first use of a given template.
Fixes the problem identified in #1396 .
2019-09-27 18:34:12 +02:00
Eddie Hung
7c8de1dd18
Hell let's add the original #1381 testcase too
2019-09-20 17:58:51 -07:00
Eddie Hung
6258e6a7e2
Add testcase
2019-09-20 17:51:45 -07:00
Marcin Kościelnicki
c9f9518de4
Added extractinv pass
2019-09-19 04:02:48 +02:00
Marcin Kościelnicki
f72765090c
Add -match-init option to dff2dffs.
2019-09-11 19:38:20 +02:00
Marcin Kościelnicki
a82e8df7d3
techmap: Add support for extracting init values of ports
2019-09-07 16:30:43 +02:00
Marcin Kościelnicki
5fb4b12cb5
improve clkbuf_inhibit propagation upwards through hierarchy
2019-08-27 17:26:47 +02:00
Eddie Hung
528f1c8687
Improve tests to check that clkbuf is connected to expected
2019-08-26 13:45:16 -07:00
Eddie Hung
a0d85393e3
Check clkbuf_inhibit=1 is ignored for custom selection
2019-08-23 11:15:26 -07:00
Eddie Hung
5628e2ec53
Add simple clkbufmap tests
2019-08-23 11:10:02 -07:00
Eddie Hung
d62c10d641
tests/techmap/run-test.sh to cope with *.ys
2019-08-23 11:09:50 -07:00
Eddie Hung
fce8dc7db2
Add test
2019-08-20 20:05:16 -07:00
Clifford Wolf
924d9d6e86
Added read-enable to memory model
2015-09-25 12:23:11 +02:00
Clifford Wolf
dcf2e24240
Added $meminit support to "memory" command
2015-02-14 12:55:03 +01:00
Clifford Wolf
73a345294a
Changed tests/techmap/mem_simple_4x1_map for new $mem/$memwr WR_EN interface
2014-07-16 14:08:51 +02:00
Clifford Wolf
bada3ee815
Fixed yosys path in tests/techmap/mem_simple_4x1_runtest.sh
2014-03-11 11:59:58 +01:00
Clifford Wolf
4fd1a4c12b
Use "verilog -noattr" in tests/techmap/mem_simple_4x1 test (for old iverilog)
2014-03-11 11:39:30 +01:00
Clifford Wolf
3c5e973092
Use private namespace in mem_simple_4x1_map
2014-02-21 12:14:38 +01:00
Clifford Wolf
81b3f52519
Added tests/techmap/mem_simple_4x1
2014-02-21 12:06:40 +01:00