Clifford Wolf
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e164edc8d1
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Fixed typo in RTLIL::Module::addAdff()
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2014-03-17 14:41:41 +01:00 |
Clifford Wolf
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ef1795a1e8
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Fixed typo in RTLIL::Module::{addSshl,addSshr}
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2014-03-15 22:52:10 +01:00 |
Clifford Wolf
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b7c71d92f6
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Added RTLIL::Module::add{Dff,Dffsr,Adff,Dlatch}Gate() API
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2014-03-15 14:35:29 +01:00 |
Clifford Wolf
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0ac915a757
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Progress in Verific bindings
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2014-03-14 11:46:13 +01:00 |
Clifford Wolf
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77e5968323
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Added RTLIL::Module::Add{Inv,And,Or,Xor,Mux}Gate API
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2014-03-14 11:45:44 +01:00 |
Clifford Wolf
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fad8558eb5
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Merged OSX fixes from Siesh1oo with some modifications
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2014-03-13 12:48:10 +01:00 |
Clifford Wolf
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78c64a6401
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Fixed a typo in RTLIL::Module::addReduce...
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2014-03-10 12:07:26 +01:00 |
Clifford Wolf
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fdef064b1d
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Added RTLIL::Module::add... helper methods
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2014-03-10 03:02:27 +01:00 |
Clifford Wolf
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8f9c707a4c
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Improved checking of internal cell conventions
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2014-02-08 19:13:49 +01:00 |
Clifford Wolf
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fc3b3c4ec3
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Added $slice and $concat cell types
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2014-02-07 17:44:57 +01:00 |
Clifford Wolf
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a1ac710ab8
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Stronger checking of internal cells
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2014-02-07 17:39:35 +01:00 |
Clifford Wolf
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fa295a4528
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Added generic RTLIL::SigSpec::parse_sel() with support for selection variables
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2014-02-06 19:22:46 +01:00 |
Clifford Wolf
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a6750b3753
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Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)
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2014-02-03 13:01:45 +01:00 |
Clifford Wolf
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f9c4d33909
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Added RTLIL::SigSpec::to_single_sigbit()
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2014-02-02 21:35:26 +01:00 |
Clifford Wolf
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1e67099b77
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Added $assert cell
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2014-01-19 14:03:40 +01:00 |
Clifford Wolf
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eec2cd1e78
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Added RTLIL::SigSpec::optimized() API
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2014-01-03 02:43:31 +01:00 |
Clifford Wolf
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fb2bf934dc
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Added correct handling of $memwr priority
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2014-01-03 00:22:17 +01:00 |
Clifford Wolf
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15acf593e7
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Added additional checks for A_SIGNED == B_SIGNED for cells with that constraint
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2013-12-31 14:54:06 +01:00 |
Clifford Wolf
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c69c416d28
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Added $bu0 cell (for easy correct $eq/$ne mapping)
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2013-12-28 12:02:14 +01:00 |
Clifford Wolf
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369bf81a70
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Added support for non-const === and !== (for miter circuits)
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2013-12-27 14:20:15 +01:00 |
Clifford Wolf
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5d83904746
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Fixes and improvements in RTLIL::SigSpec::parse
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2013-12-07 11:57:29 +01:00 |
Clifford Wolf
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f4b46ed31e
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Replaced signed_parameters API with CONST_FLAG_SIGNED
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2013-12-04 14:24:44 +01:00 |
Clifford Wolf
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93a70959f3
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Replaced RTLIL::Const::str with generic decoder method
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2013-12-04 14:14:05 +01:00 |
Clifford Wolf
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f71e27dbf1
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Remove auto_wire framework (smarter than the verilog standard)
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2013-11-24 17:29:11 +01:00 |
Clifford Wolf
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609caa23b5
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Implemented correct handling of signed module parameters
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2013-11-24 17:17:21 +01:00 |
Clifford Wolf
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18d003254c
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Massive performance improvement from refactoring RTLIL::SigSpec::optimize()
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2013-11-22 04:41:20 +01:00 |
Clifford Wolf
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8e58bb330d
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Added SigBit struct and refactored RTLIL::SigSpec::extract
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2013-11-22 04:07:13 +01:00 |
Clifford Wolf
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0fd3ebdb23
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Added information on all internal cell types to internal checker
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2013-11-11 00:13:18 +01:00 |
Clifford Wolf
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223892ac28
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Improved user-friendliness of "sat" and "eval" expression parsing
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2013-11-09 12:02:27 +01:00 |
Clifford Wolf
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947bd9b96b
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Renamed extend_un0() to extend_u0() and use it in genrtlil
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2013-11-07 18:17:10 +01:00 |
Clifford Wolf
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0e1661f84e
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Fixed type of sign extension in opt_const $eq/$ne handling
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2013-11-07 16:53:28 +01:00 |
Clifford Wolf
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f94266bb42
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Added eval -vloghammer_report mode
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2013-11-06 04:14:56 +01:00 |
Clifford Wolf
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8e8f1994b8
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Changed NEW_WIRE API to return the wire, not the signal
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2013-10-18 14:19:45 +02:00 |
Clifford Wolf
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cc5e379eca
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Added RTLIL NEW_WIRE macro
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2013-10-18 13:25:24 +02:00 |
Clifford Wolf
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0f38008ed3
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Added "design" command (-reset, -save, -load)
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2013-07-27 14:27:51 +02:00 |
Clifford Wolf
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21e38bed98
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Added "eval" pass
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2013-06-19 09:30:37 +02:00 |
Clifford Wolf
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6971c4db62
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Added RTLIL::Module::fixup_ports() API and RTLIL::*::rewrite_sigspecs() API
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2013-06-18 17:11:13 +02:00 |
Clifford Wolf
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21d9251e52
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Added "dump" command (part ilang backend)
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2013-06-02 17:53:30 +02:00 |
Clifford Wolf
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88af5b6a16
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Improved opt_share for reduce cells
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2013-03-29 11:19:21 +01:00 |
Clifford Wolf
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041c06bd9d
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Create nice errors when calling RTLIL::Module::derive() of base class
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2013-03-26 19:27:49 +01:00 |
Clifford Wolf
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7764d0ba1d
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initial import
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2013-01-05 11:13:26 +01:00 |