Marcin Kościelnicki
aff6ad1ce0
xilinx: Improve flip-flop handling.
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This adds support for infering more kinds of flip-flops:
- FFs with async set/reset and clock enable
- FFs with sync set/reset
- FFs with sync set/reset and clock enable
Some passes have been moved (and some added) in order for dff2dffs to
work correctly.
This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop
capabilities (though not latch capabilities). Older FPGAs also support
having both a set and a reset input, which will be handled at a later
data.
2019-12-18 13:43:43 +01:00
Marcin Kościelnicki
fcce94010f
xilinx: Add tristate buffer mapping. ( #1528 )
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Fixes #1225 .
2019-12-04 09:44:00 +01:00
Eddie Hung
be9e4f1b67
Use abc_{map,unmap,model}.v
2019-08-20 12:39:11 -07:00
David Shah
ab607e896e
xilinx: Fix missing cell name underscore in cells_map.v
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Signed-off-by: David Shah <dave@ds0.me>
2019-07-25 08:19:07 +01:00
Eddie Hung
58bb84e5b2
Add some spacing
2019-07-10 12:32:33 -07:00
Eddie Hung
521971e32e
Add some ASCII art explaining mux decomposition
2019-07-10 12:20:04 -07:00
Eddie Hung
b1a048a703
Extend using A[1] to preserve don't care
2019-07-09 12:35:41 -07:00
Eddie Hung
93522b0ae1
Extend during mux decomposition with 1'bx
2019-07-09 10:59:37 -07:00
Eddie Hung
c864995343
Fix typo and comments
2019-07-09 10:38:07 -07:00
Eddie Hung
c91cb73562
Merge remote-tracking branch 'origin/master' into xc7mux
2019-07-09 10:22:49 -07:00
Eddie Hung
6951e32070
Decompose mux inputs in delay-orientated (rather than area) fashion
2019-07-08 23:51:13 -07:00
Eddie Hung
d4ab43d940
Add one more comment
2019-07-08 23:05:48 -07:00
Eddie Hung
939a225f92
Less thinking
2019-07-08 23:02:57 -07:00
Eddie Hung
de40453553
Reword
2019-07-08 22:56:19 -07:00
Eddie Hung
3f86407cc3
Map $__XILINX_SHIFTX in a more balanced manner
2019-07-08 17:06:35 -07:00
Eddie Hung
895ca50173
Fixes for 2:1 muxes
2019-07-08 12:03:38 -07:00
Eddie Hung
09ac274716
Revert "Fix broken MUXFx box, use MUXF7x2 box instead"
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This reverts commit a9a140aa6c
.
2019-07-01 14:01:09 -07:00
Eddie Hung
a9a140aa6c
Fix broken MUXFx box, use MUXF7x2 box instead
2019-07-01 13:36:27 -07:00
Eddie Hung
85f1c2dcbe
Cleanup SRL inference/make more consistent
2019-06-29 21:42:20 -07:00
Eddie Hung
62ba724ccb
Merge remote-tracking branch 'origin/master' into xc7mux
2019-06-29 19:39:27 -07:00
Eddie Hung
ea0f7c9be9
Restore $__XILINX_MUXF78 const optimisation
2019-06-28 12:12:41 -07:00
Eddie Hung
a193bf27c9
Clean up trimming leading 1'bx in A during techmappnig
2019-06-28 12:03:43 -07:00
Eddie Hung
4ef26d4755
Merge remote-tracking branch 'origin/master' into xc7mux
2019-06-28 11:09:42 -07:00
Eddie Hung
00f63d82ce
Reduce diff with upstream
2019-06-27 16:13:22 -07:00
Eddie Hung
4238feed81
This optimisation doesn't seem to work...
2019-06-25 09:21:46 -07:00
Eddie Hung
c3df895bf4
Reduce MuxFx resources in mux techmapping
2019-06-24 15:16:44 -07:00
Eddie Hung
db6a0b72b2
Reduce number of decomposed muxes during techmap
2019-06-24 14:28:56 -07:00
Eddie Hung
2e7992efff
Revert "Fix techmapping muxes some more"
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This reverts commit 0aae3b4f43
.
2019-06-24 14:15:31 -07:00
Eddie Hung
0aae3b4f43
Fix techmapping muxes some more
2019-06-24 12:50:48 -07:00
Eddie Hung
2b4501503d
Fix mux techmapping
2019-06-24 12:18:17 -07:00
Eddie Hung
36e6da5396
Change synth_xilinx's -nomux to -minmuxf <int>
2019-06-24 10:04:01 -07:00
Eddie Hung
8bce3fb329
Fix spacing
2019-06-21 16:55:34 -07:00
Eddie Hung
9abde12110
Add $__XILINX_MUXF78 to preserve entire box
2019-06-21 15:47:42 -07:00
Eddie Hung
b63b2a0bd4
Revert "Remove wide mux inference"
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This reverts commit 738fdfe8f5
.
2019-06-14 12:50:24 -07:00
Eddie Hung
75d89e56cf
Fix name clash
2019-06-13 14:27:07 -07:00
Eddie Hung
009255d11d
Move neg-pol to pos-pol mapping from ff_map to cells_map.v
2019-06-12 16:07:24 -07:00
Eddie Hung
738fdfe8f5
Remove wide mux inference
2019-06-12 09:20:46 -07:00
Eddie Hung
88ae13e6a5
$__XILINX_MUX_ -> $__XILINX_SHIFTX
2019-06-06 15:32:36 -07:00
Eddie Hung
d3b7ae218b
Fix muxcover and its techmapping
2019-06-06 15:31:18 -07:00
Eddie Hung
a8c49168fb
Run muxpack and muxcover in synth_xilinx
2019-06-06 14:43:08 -07:00
Eddie Hung
67f744d428
Cleanup
2019-06-05 12:28:46 -07:00
Eddie Hung
6cf092641f
Fix name clash
2019-06-04 09:56:36 -07:00
Eddie Hung
e260150321
Add mux_map.v for wide mux
2019-06-04 09:51:47 -07:00
Eddie Hung
9b1078b9bd
Fix/workaround symptom unveiled by #1023
2019-05-21 18:50:02 -07:00
Eddie Hung
fb09c6219b
Merge remote-tracking branch 'origin/master' into xc7mux
2019-05-21 14:21:00 -07:00
Eddie Hung
c2e29ab809
Rename cells_map.v to prevent clash with ff_map.v
2019-05-03 14:40:32 -07:00
Eddie Hung
283e33ba5a
Trim off leading 1'bx in A
2019-05-02 16:02:37 -07:00
Eddie Hung
fc72f07efd
Add don't care optimisation
2019-05-02 15:01:37 -07:00
Eddie Hung
95867109ea
Revert to pre-muxcover approach
2019-05-02 11:25:10 -07:00
Eddie Hung
5cd19b52da
Merge remote-tracking branch 'origin/master' into xc7mux
2019-05-02 10:44:59 -07:00