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11197 Commits

Author SHA1 Message Date
github-actions[bot] 675a7bd22c Bump version 2022-02-03 00:54:22 +00:00
Miodrag Milanović 2d98fe870c
Merge pull request #3183 from YosysHQ/micko/nto1mux 
Use bmux for NTO1MUX
 2022-02-02 16:22:53 +01:00
Miodrag Milanovic 0b633b6c2e Use bmux for NTO1MUX 2022-02-02 16:16:08 +01:00
Miodrag Milanović 518521c72e
Merge pull request #3182 from yrabbit/wip-doc2 
Correct a typo in the manual
 2022-02-02 12:19:17 +01:00
YRabbit f5609d52c4 Correct a typo in the manual 
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2022-02-02 21:14:38 +10:00
Scott Thibault 0a6e2bd5d5 Update comment 2022-02-02 03:21:09 +01:00
Scott Thibault e04ac4e9e9 Fix unextend method for signed constants 2022-02-02 03:21:09 +01:00
Miodrag Milanović bf85dfee5e
Merge pull request #3176 from higuoxing/fix-ref-manual 
Fix the help message of synth_quicklogic command.
 2022-01-31 16:11:00 +01:00
github-actions[bot] fc40df0916 Bump version 2022-01-31 00:54:31 +00:00
Marcelina Kościelnicka 56e7791760 verilog backend: Emit a `wire` for ports as well. 
Fixes #3177.
 2022-01-31 01:08:41 +01:00
Xing GUO 0520e99968 Fix the help message of synth_quicklogic. 2022-01-31 02:23:59 +08:00
Marcelina Kościelnicka 07a657fb0c opt_reduce: Add $bmux and $demux optimization patterns. 2022-01-30 03:37:52 +01:00
github-actions[bot] 772d137bfa Bump version 2022-01-29 02:48:50 +00:00
Marcelina Kościelnicka 93508d58da Add $bmux and $demux cells. 2022-01-28 23:34:41 +01:00
Marcelina Kościelnicka db33b1e535 opt_dff: Don't mutate muxes while ModWalker is active. 2022-01-28 08:55:56 +01:00
Marcelina Kościelnicka bac750fb99 kernel/mem: Add read-first semantic emulation code. 2022-01-28 08:48:33 +01:00
github-actions[bot] 9a2294f285 Bump version 2022-01-28 02:39:40 +00:00
Marcelina Kościelnicka 0e97c3fd74 manual: Fix a custom pass example. 
Fixes #3156.
 2022-01-27 23:27:45 +01:00
Marcelina Kościelnicka 1759c80a3f memory_bram: Make use of new mem emulation functions to map more RAMs. 2022-01-27 19:31:27 +01:00
Marcelina Kościelnicka 5e4c6915c9 kernel/mem: Add functions to emulate read port enable/init/reset signals. 2022-01-27 19:28:07 +01:00
github-actions[bot] 84f0df1c95 Bump version 2022-01-27 00:56:19 +00:00
Miodrag Milanović 76f7b030ae
change to windows-2019 2022-01-26 18:00:41 +01:00
github-actions[bot] bc027b2cae Bump version 2022-01-20 01:06:01 +00:00
gatecat f699c4ba58 nexus: Fix BB sim model 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-01-19 18:14:24 +00:00
Miodrag Milanovic 36482680d5 Removed dbits 8 since 9 will always be picked 2022-01-19 08:51:25 +01:00
Miodrag Milanović 4525e419f6
Merge pull request #3120 from Icenowy/anlogic-bram 
anlogic: support BRAM mapping
 2022-01-19 08:49:58 +01:00
github-actions[bot] 59382945a9 Bump version 2022-01-18 01:00:53 +00:00
Miodrag Milanović 55924de708
Merge pull request #3162 from YosysHQ/mmicko/windows_guidelines 
Add info about VS build
 2022-01-17 13:20:45 +01:00
Miodrag Milanović 703306c119
Update guidelines/Windows 
Co-authored-by: N. Engelhardt <nakengelhardt@gmail.com>
 2022-01-17 13:11:15 +01:00
N. Engelhardt 891eec2882
Merge pull request #3145 from nakengelhardt/advertise_suite_in_readme 
mention tabby+oss cad suite in readme
 2022-01-17 12:50:53 +01:00
N. Engelhardt 15b4d05805 mention distributions' package manager 2022-01-17 12:49:32 +01:00
Miodrag Milanović 41e215219b
Add info about VS build 2022-01-17 10:07:56 +01:00
github-actions[bot] 61324cf55f Bump version 2022-01-12 00:59:23 +00:00
Miodrag Milanovic b91533d9f2 Forgot one 2022-01-11 09:39:45 +01:00
Miodrag Milanovic 883b4fb7e6 Change url to https 2022-01-11 08:56:33 +01:00
Miodrag Milanovic c428a894c0 Next dev cycle 2022-01-11 08:39:34 +01:00
Miodrag Milanovic 8b1eafc3ad Release version 0.13 2022-01-11 08:35:50 +01:00
Miodrag Milanovic 64972360a8 Update CHANGELOG 2022-01-11 08:21:12 +01:00
github-actions[bot] 0feba821a8 Bump version 2022-01-09 01:01:33 +00:00
Zachary Snow aa35f24290 sv: auto add nosync to certain always_comb local vars 
If a local variable is always assigned before it is used, then adding
nosync prevents latches from being needlessly generated.
 2022-01-07 22:53:22 -07:00
Zachary Snow 828e85068f sv: fix size cast internal expression extension 2022-01-07 21:21:02 -07:00
github-actions[bot] 59a7150344 Bump version 2022-01-05 01:00:24 +00:00
Zachary Snow 66447e8faf logger: fix unmatched expected warnings and errors 
- Prevent unmatched expected error patterns from self-matching
- Prevent infinite recursion on unmatched expected warnings
- Always print the error message for unmatched error patterns
- Add test coverage for all unmatched message types
- Add test coverage for excess matched logs and warnings
 2022-01-04 13:39:34 -07:00
Austin Seipp b022fe61a7 opt_dff: fix sequence point copy paste bug 
Newer GCCs emit the following warning for opt_dff:

    passes/opt/opt_dff.cc:560:17: warning: operation on ‘ff.Yosys::FfData::has_clk’ may be undefined [-Wsequence-point]
      560 |      ff.has_clk = ff.has_ce = ff.has_clk = false;
          |      ~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Which is correct: the order of whether the read or write of has_clk
occurs first is undefined since there is no sequence point between them.

This is almost certainly just a typo/copy paste error and objectively
wrong, so just fix it.

Signed-off-by: Austin Seipp <aseipp@pobox.com>
 2022-01-04 18:18:08 +01:00
N. Engelhardt 6483e691bc mention tabby+oss cad suite in readme 2022-01-04 15:44:37 +01:00
gatecat 493b5e03e7 manual: Fix cell-stmt order 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-01-03 18:17:10 -07:00
github-actions[bot] 361916ad3e Bump version 2022-01-04 00:58:28 +00:00
Zachary Snow e0e4dfb55e fix iverilog compatibility for new case expr tests 2022-01-03 12:11:41 -07:00
Zachary Snow 207af4196b fixup verilog doubleslash test 
- add generated doubleslash.v to .gitignore
- ensure backend verilog can be read again
 2022-01-03 08:17:46 -07:00
Zachary Snow 8c509a5659 sv: fix size cast clipping expression width 2022-01-03 08:17:35 -07:00