4a2fb18718
Changes in libs, passes and tests Makefiles. LDLIBS -> LIBS. LDFLAGS -> LINKFLAGS. CXX is clang++ or g++, not clang and gcc
2024-02-25 17:23:56 +01:00
033fa10307
We use CXX instead of LD for linking yosys-filterlib
2024-02-25 16:49:28 +01:00
03cadf6474
dfflibmap: use patmatch() from kernel/yosys.cc
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Replace OS matching functions with yosys kernel function
Signed-off-by: Austin Rovinski <rovinski@nyu.edu>
2024-02-20 11:04:55 -05:00
bc8a3a5b18
Merge pull request #4219 from rovinski/master
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dfflibmap: Add a -dont_use flag to ignore cells
2024-02-20 12:43:44 +01:00
a3c81f4d62
Merge pull request #4216 from YosysHQ/show_href
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show: Add option to add cell/wire "src" attribute into graphviz attribute href
2024-02-19 20:50:53 +01:00
5059bb1d4f
dfflibmap: force PathMatchSpecA on WIN32
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Depending on the WIN32 compilation mode, PathMatchSpec may expect a LPCSTR or
LPCWSTR argument. char* is only convertable to LPCSTR, so use that
implementation
Signed-off-by: Austin Rovinski <rovinski@nyu.edu>
2024-02-19 14:40:46 -05:00
689feed012
dfflibmap: Add a -dont_use flag to ignore cells
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This is an alternative to setting the dont_use property in lib. This brings
dfflibmap in parity with the abc pass for dont_use.
Signed-off-by: Austin Rovinski <rovinski@nyu.edu>
2024-02-19 13:00:18 -05:00
db947e4c71
Merge pull request #4218 from kivikakk/proc_rom-actionless-switch
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proc_rom: don't assert on big actionless switch.
2024-02-19 16:21:40 +01:00
4b99db0b73
Merge pull request #4177 from povik/connect-extra_args
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connect: Do interpret selection arguments
2024-02-19 15:18:37 +01:00
aebb7a0c4d
Merge pull request #4188 from povik/dlatch-bwmux
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proc_dlatch: Include `$bwmux` among considered mux cells
2024-02-19 15:15:03 +01:00
bf4a46ccb3
proc_rom: don't assert on big actionless switch.
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See the test case. PROC_ROM will consider this for evaluation, even
though -- without any actions -- lhs is empty (but still "uniform").
A zero-width memory is constructed, which later fails check with:
ERROR: Assert `width != 0' failed in kernel/mem.cc:518.
Ensure we don't proceed if there's nothing to encode.
2024-02-18 01:33:28 +11:00
61b3b9b58a
Merge pull request #4197 from QuantamHD/sequential_area
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stat: Add sequential area output to stat -liberty
2024-02-16 19:15:44 +01:00
b8a1009de9
Update passes/cmds/stat.cc
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Make reporting line more clear about the non cumulative area of sequential cells
Co-authored-by: N. Engelhardt <nakengelhardt@gmail.com>
2024-02-16 07:44:09 -08:00
f0df0e3912
update type and variable names
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Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
2024-02-16 00:01:44 +00:00
2d8343d423
update type and variable names
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Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
2024-02-15 23:59:19 +00:00
bbdfcfdf30
clk2fflogic: Fix handling of $check cells
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Fixes a bug in the handling of the recently introduced $check cells.
Both $check and $print cells in clk2fflogic are handled by the same code
and the existing tests for that were only using $print cells. This
missed a bug where the additional A signal of $check cells that is not
present on $print cells was dropped due to a typo, rendering $check
cells non-functional.
Also updates the tests to explicitly cover both cell types such that
they would have detected the now fixed bug.
2024-02-14 11:42:27 +01:00
834276a2f7
show: Add option to add cell/wire "src" attribute into graphviz attribute href
2024-02-14 09:50:53 +01:00
edb95c69a9
Merge pull request #4084 from jix/scopeinfo
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$scopeinfo support
2024-02-12 09:51:22 +01:00
8566489d85
stat: Add sequential area output to stat -liberty
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Checks to see if a cell is of type ff in the liberty,
and keeps track of an additional area value.
```
Chip area for module '\addr': 92.280720
Sequential area for module '\addr': 38.814720
```
Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
2024-02-09 23:51:00 +00:00
2f4c917dac
Merge pull request #4181 from povik/ci-cxxstd-fix
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ci: Fix CXXSTD typo
2024-02-08 18:55:47 +01:00
043f1e2bcb
opt_lut: Remove leftover `-dlogic` help
2024-02-08 17:49:44 +01:00
af1a5cfeb9
Address `SigBit`/`SigSpec` confusion issues under c++20
2024-02-08 17:48:36 +01:00
862f2fd705
proc_dlatch: Include `$bwmux` among considered mux cells
2024-02-08 00:08:50 +01:00
bfd9cf63db
Ignore $scopeinfo in opt_merge
2024-02-06 17:51:29 +01:00
8902fc94b6
Suport $scopeinfo in flatten and opt_clean
2024-02-06 17:51:29 +01:00
269c50f90e
Merge pull request #4130 from jix/hierarchy-defer-notop
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hierarchy: Without a known top module, derive all deferred modules
2024-02-06 12:08:01 +01:00
0470cbb00d
hierarchy: Without a known top module, derive all deferred modules
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This fixes hierarchy when used with cell libraries that were loaded with
-defer and also makes more of the hierarchy visible to the auto-top
heuristic.
2024-02-06 10:31:40 +01:00
1b73b5beb7
Merge pull request #4174 from YosysHQ/claire/overwrite
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Add API to overwrite existing pass from plugin
2024-02-05 23:49:24 +01:00
f96e27ac14
Merge pull request #4123 from povik/clean-opt_clean
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opt_clean: Add commentary, remove dead code
2024-02-05 15:08:34 +01:00
c7bf0e3b8f
Add new `$check` cell to represent assertions with a message.
2024-02-01 20:10:39 +01:00
e1a59ba80b
async2sync, clk2fflogic: Add support for $check and $print cells
2024-02-01 20:10:39 +01:00
6c4902313b
chformal: Support $check cells and add chformal -lower
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This adds support for `$check` cells in chformal and adds a `-lower`
mode which converts `$check` cells into `$assert` etc. cells with a
`$print` cell to output the `$check` message.
2024-02-01 20:10:39 +01:00
a84fa0a277
connect: Do interpret selection arguments
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Instead of silently ignoring what would ordinarily be the selection
arguments to a pass, interpret those and mark the support in the help
message.
2024-02-01 10:28:36 +01:00
6c4bc5aae5
Merge pull request #4165 from phsauter/shiftadd-offset-fix
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peepopt: handle offset too large in `shiftadd`
2024-01-31 13:47:39 +01:00
cbdf9b2f9c
peepopt: handle empty src-attribute in shiftadd
2024-01-31 13:07:01 +01:00
4fa314c0bd
Add API to overwrite existing pass from plugin
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2024-01-30 17:51:11 +01:00
7f8b6dd982
peepopt: delete unnecessary comment in shiftadd
2024-01-30 09:51:21 +01:00
7afc0696e2
opt_clean: Assert an impossible path isn't taken
2024-01-29 11:26:44 +01:00
ec065186d3
opt_clean: Add commentary around wire cleaning, NFC
2024-01-29 11:26:44 +01:00
68a9aa7c29
peepopt: handle offset too large in `shiftadd`
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If the offset is larger than the signal itself,
meaning the signal is completely shifted out,
it tried to extract a negative amount of bits from the old signal.
This RTL pattern is suspicious since it is a complicated way of
arriving at a constant value, so we warn the user.
2024-01-26 16:44:30 +01:00
7c818d30f7
sim: Bring $print trigger/sampling semantics in line with FFs
2024-01-25 16:21:03 +01:00
3d9e44d182
hierarchy: keep display statements, like formal assertions.
2024-01-22 10:09:22 +00:00
b3e7390c0e
Fix typo in stat help
2024-01-21 16:32:05 -05:00
e1f4c5c9cb
Merge pull request #4133 from YosysHQ/show_color_proc
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show: allow setting colors via selection on PROC boxes
2024-01-17 17:56:53 +01:00
6a7fad4dd9
Merge pull request #4132 from povik/opt_lut_ice40
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opt_lut: Replace `-dlogic` with `-tech ice40`
2024-01-17 14:26:28 +01:00
fb4eeb1344
show: allow setting colors via selection on PROC boxes
2024-01-15 17:47:59 +01:00
149bcd88ad
Merge pull request #4026 from uis246/fix-format
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Fix printf formats
2024-01-15 16:04:11 +01:00
568418b50b
opt_lut: Replace `-dlogic` with `-tech ice40`
2024-01-15 12:35:21 +01:00
5902b2826d
Fix printf formats
2024-01-15 12:07:54 +01:00
acf916f654
Restore sim output from initial $display
2024-01-14 16:52:51 +01:00
Roland Coeurjoly
Austin Rovinski
Miodrag Milanović
Martin Povišer
N. Engelhardt
Amelia Cuss
Ethan Mahintorabi
Ethan Mahintorabi
Jannis Harder
Claire Xen
Catherine
Philippe Sauter
Stephen Tong
uis
Dag Lem