Clifford Wolf
|
0bc95f1e04
|
Added "yosys -D" feature
|
2016-04-21 23:28:37 +02:00 |
Clifford Wolf
|
207736b4ee
|
Import more std:: stuff into Yosys namespace
|
2015-10-25 19:30:49 +01:00 |
Clifford Wolf
|
84bf862f7c
|
Spell check (by Larry Doolittle)
|
2015-08-14 10:56:05 +02:00 |
Clifford Wolf
|
6c84341f22
|
Fixed trailing whitespaces
|
2015-07-02 11:14:30 +02:00 |
Clifford Wolf
|
4e6ca7760f
|
Replaced ezDefaultSAT with ezSatPtr
|
2015-02-21 12:15:41 +01:00 |
Clifford Wolf
|
fe829bdbdc
|
Added log_warning() API
|
2014-11-09 10:44:23 +01:00 |
Clifford Wolf
|
7cb0d3aa1a
|
Renamed TRUE/FALSE to CONST_TRUE/CONST_FALSE because of name collision on Win32
|
2014-10-10 17:07:24 +02:00 |
Clifford Wolf
|
4569a747f8
|
Renamed SIZE() to GetSize() because of name collision on Win32
|
2014-10-10 17:07:24 +02:00 |
Clifford Wolf
|
f9a307a50b
|
namespace Yosys
|
2014-09-27 16:17:53 +02:00 |
Clifford Wolf
|
b9bd22b8c8
|
More cleanups related to RTLIL::IdString usage
|
2014-08-02 13:19:57 +02:00 |
Clifford Wolf
|
10e5791c5e
|
Refactoring: Renamed RTLIL::Design::modules to modules_
|
2014-07-27 11:18:30 +02:00 |
Clifford Wolf
|
4c4b602156
|
Refactoring: Renamed RTLIL::Module::cells to cells_
|
2014-07-27 01:51:45 +02:00 |
Clifford Wolf
|
f9946232ad
|
Refactoring: Renamed RTLIL::Module::wires to wires_
|
2014-07-27 01:49:51 +02:00 |
Clifford Wolf
|
c094c53de8
|
Removed RTLIL::SigSpec::optimize()
|
2014-07-23 20:32:28 +02:00 |
Clifford Wolf
|
a62c21c9c6
|
Removed RTLIL::SigSpec::expand() method
|
2014-07-23 19:34:51 +02:00 |
Clifford Wolf
|
4e802eb7f6
|
Fixed all users of SigSpec::chunks_rw() and removed it
|
2014-07-23 15:36:09 +02:00 |
Clifford Wolf
|
ec923652e2
|
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3
|
2014-07-23 09:52:55 +02:00 |
Clifford Wolf
|
a8d3a68971
|
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3
|
2014-07-23 09:49:43 +02:00 |
Clifford Wolf
|
28b3fd05fa
|
SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()
|
2014-07-22 20:58:44 +02:00 |
Clifford Wolf
|
4b4048bc5f
|
SigSpec refactoring: using the accessor functions everywhere
|
2014-07-22 20:39:37 +02:00 |
Clifford Wolf
|
a233762a81
|
SigSpec refactoring: renamed chunks and width to __chunks and __width
|
2014-07-22 20:39:37 +02:00 |
Clifford Wolf
|
fa295a4528
|
Added generic RTLIL::SigSpec::parse_sel() with support for selection variables
|
2014-02-06 19:22:46 +01:00 |
Clifford Wolf
|
249ef8695a
|
Major rewrite of "freduce" command
|
2014-01-02 16:52:33 +01:00 |
Clifford Wolf
|
5de57e9970
|
Fixed compiler warining in passes/sat/eval.cc
|
2013-12-07 16:19:24 +01:00 |
Clifford Wolf
|
325b764341
|
Added eval -set-undef and eval -table
|
2013-12-07 11:58:22 +01:00 |
Clifford Wolf
|
61412d167f
|
Improvements in satgen undef handling
|
2013-11-25 16:50:45 +01:00 |
Clifford Wolf
|
bd65e67d8a
|
Improvements in satgen undef handling
|
2013-11-25 15:12:01 +01:00 |
Clifford Wolf
|
8c3f4b3957
|
Started implementing undef handling in satgen
|
2013-11-25 04:51:33 +01:00 |
Clifford Wolf
|
223892ac28
|
Improved user-friendliness of "sat" and "eval" expression parsing
|
2013-11-09 12:02:27 +01:00 |
Clifford Wolf
|
18f9477e95
|
Added verification of SAT model to "eval -vloghammer_report" command
|
2013-11-09 11:38:17 +01:00 |
Clifford Wolf
|
f485962c5e
|
Added handling of unconnected/unspecified signals to eval -vloghammer_report
|
2013-11-06 22:42:07 +01:00 |
Clifford Wolf
|
031a91dc94
|
Added correct RTL undef handling to eval vloghammer mode
|
2013-11-06 13:16:47 +01:00 |
Clifford Wolf
|
f94266bb42
|
Added eval -vloghammer_report mode
|
2013-11-06 04:14:56 +01:00 |
Clifford Wolf
|
d0e93e04d1
|
Added eval -brute_force_equiv_checker_x mode
|
2013-08-15 11:09:30 +02:00 |
Clifford Wolf
|
21e38bed98
|
Added "eval" pass
|
2013-06-19 09:30:37 +02:00 |