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3,101 Commits 76 Branches 48 Tags 62 MiB
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234 Commits

Author SHA1 Message Date
Clifford Wolf b1cdf772eb Added "design -reset-vlog" 2016-11-30 11:25:55 +01:00
Clifford Wolf e444e59963 Added wire start_offset and upto handling to splitnets cmd 2016-11-23 13:54:33 +01:00
Clifford Wolf 97ac77513f Bugfix in "setundef" pass 2016-11-08 18:53:36 +01:00
Clifford Wolf ef603c6fe1 Implemented "scc -set_attr" 2016-11-06 00:04:10 +01:00
Clifford Wolf 914aa8a5d3 Bugfix in "scc" command 2016-11-06 00:03:35 +01:00
Clifford Wolf 3655d7fea7 Added "setparam -type" 2016-10-19 13:54:04 +02:00
Clifford Wolf f3f5a02045 Added "tee +INT -INT" 2016-09-06 17:43:24 +02:00
Clifford Wolf 66582964bc Improved "show" help message 2016-08-28 12:34:36 +02:00
Clifford Wolf 321e15b0bf Minor fixes in show command 2016-08-16 00:36:24 +02:00
Clifford Wolf 6ed6b3cb6d Replaced "select -assert-limit" with -assert-max and -assert-min 2016-07-01 12:24:13 +02:00
eshellko 9a742f4069 Added 'assert-limit' option for 'select' command 
For resource limited designs such as FPGA it can be useful to specify limit of specific resources available on board. So user can check if he should change RTL as early as mapping done.
 2016-07-01 10:24:22 +04:00
Clifford Wolf dcf576641b Added "setundef -init" 2016-06-03 11:38:31 +02:00
Clifford Wolf 611f121cb9 Fixed "scc" for cells that have feedback singals _and_ are part of a larger loop 2016-05-27 16:33:13 +02:00
Clifford Wolf e01464e2ac Added "qwp -v" 2016-04-28 23:17:30 +02:00
Clifford Wolf 0bc95f1e04 Added "yosys -D" feature 2016-04-21 23:28:37 +02:00
Clifford Wolf a47f69536a Added support for installed plugins 2016-03-30 10:02:03 +02:00
Clifford Wolf 2c7e107d7a Support for abstract modules in chparam 2016-03-21 16:37:35 +01:00
Clifford Wolf 825b99efc1 Added "stat -liberty" for calculating chip area 2016-02-04 12:26:13 +01:00
Clifford Wolf 1d62f8710f Fixed "splitnets -ports" for hierarchical designs 2015-12-22 13:25:00 +01:00
Clifford Wolf ab0c44d3ed Added %R select expression 2015-12-20 13:35:58 +01:00
Clifford Wolf e61c7f887a Added torder command 2015-11-19 15:34:32 +01:00
Clifford Wolf 207736b4ee Import more std:: stuff into Yosys namespace 2015-10-25 19:30:49 +01:00
Clifford Wolf 7f110e7018 renamed SigSpec::to_single_sigbit() to SigSpec::as_bit(), added is_bit() 2015-10-24 22:56:40 +02:00
Clifford Wolf 6af8076967 improvement in "stat" 2015-10-24 21:56:53 +02:00
Clifford Wolf c35db8c19e Disabled "Skipping blackbox module" msg in show command 2015-10-23 20:11:05 +02:00
Clifford Wolf c58bd5dc30 Added edgetypes command 2015-09-27 11:53:20 +02:00
Clifford Wolf 281c1f4029 Some cleanups in qwp 2015-09-26 10:42:27 +02:00
Clifford Wolf ec92c89659 Added pivoting to qwp solver 2015-09-24 22:16:37 +02:00
Clifford Wolf 69071bbc5f Improved qwp performance 2015-09-24 21:50:37 +02:00
Clifford Wolf b1e9cb332d Added statistics summary to "qwp" 2015-09-24 21:22:24 +02:00
Clifford Wolf 11c27b5e69 Bugfix in "qwp" pass 2015-09-21 10:37:24 +02:00
Clifford Wolf 80898dcbc8 Improvements and fixes in "qwp" pass 2015-09-21 01:05:13 +02:00
Clifford Wolf 6329bea873 Added "qwp -dump" 2015-09-20 22:36:35 +02:00
Clifford Wolf 539c5eeb0f Added "qwp" command 2015-09-20 18:28:46 +02:00
Clifford Wolf 6f9a6fd783 Fixed port ordering in "splitnets" cmd 2015-09-01 13:10:36 +02:00
Larry Doolittle 6c00704a5e Another block of spelling fixes 
Smaller this time
 2015-08-14 23:27:05 +02:00
Clifford Wolf 0350074819 Re-created command-reference-manual.tex, copied some doc fixes to online help 2015-08-14 11:27:19 +02:00
Clifford Wolf 84bf862f7c Spell check (by Larry Doolittle) 2015-08-14 10:56:05 +02:00
Clifford Wolf 08ad5409a2 Some ASCII encoding fixes (comments and docs) by Larry Doolittle 2015-08-13 09:30:20 +02:00
Clifford Wolf 4d0ba9b3b2 Fixed "check" command for inout ports 2015-07-27 09:54:58 +02:00
Clifford Wolf 8393f70538 Some fixes in "select" command 2015-07-16 22:10:26 +02:00
Clifford Wolf 6c84341f22 Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
Clifford Wolf 77e89399a6 Bugfix in chparam 2015-06-30 01:38:34 +02:00
Clifford Wolf caa274ada6 Added design->rename(module, new_name) 2015-06-30 01:37:59 +02:00
Clifford Wolf 99100f367d Added "rename -top new_name" 2015-06-17 09:38:56 +02:00
Clifford Wolf 4c733301e6 Fixed cstr_buf for std::string with small string optimization 2015-06-11 13:39:49 +02:00
Clifford Wolf 96be31de89 Preserve important attributes in splitnets 2015-04-29 07:44:57 +02:00
Clifford Wolf 2fc2f8f5b3 Added "splice -wires" 2015-04-13 19:28:12 +02:00
Clifford Wolf 21a1cc1b60 Added support for "file names with blanks" 2015-04-08 12:14:34 +02:00
Clifford Wolf 8eadd8fb18 Added %M and %C select operators 2015-04-07 22:22:09 +02:00