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13558 Commits

Author SHA1 Message Date
Jannis Harder 0d30a4d479 rtlil: Add packed `extract` implementation for `SigSpec` 
Previously `extract` on a `SigSpec` would always unpack it. Since a
significant amount of `SigSpec`s have one or few chunks, it's worth
having a dedicated implementation.

This is especially true, since the RTLIL frontend calls into this for
every `wire [lhs:rhs]` slice, making this `extract` take up 40% when
profiling `read_rtlil` with one of the largest coarse grained RTLIL
designs I had on hand.

With this change the `read_rtlil` profile looks like I would expect it
to look like, but I noticed that a lot of the other core RTLIL methods
also are a bit too eager with unpacking or implementing
`SigChunk`/`Const` overloads that just convert to a single chunk
`SigSpec` and forward to the implementation for that, when a direct
implementation would avoid temporary std::vector allocations. While not
relevant for `read_rtlil`, to me it looks like there might be a few easy
overall performance gains to be had by addressing this more generally.
 2024-04-22 13:26:17 +02:00
Martin Povišer 171577f909
Merge pull request #4340 from gadfort/abc-lib-merge 
add support for using ABCs library merging when providing multiple liberty files
 2024-04-17 22:01:20 +02:00
github-actions[bot] 4897e89547 Bump version 2024-04-17 00:16:15 +00:00
Miodrag Milanović 52c04f3029
Merge pull request #4341 from YosysHQ/mmicko/ci_update 
Add new verific testing environment CI
 2024-04-16 08:30:03 +02:00
Miodrag Milanovic c38bbd7824 Add new verific testing environment CI 2024-04-16 07:50:50 +02:00
github-actions[bot] 40e8f5b69d Bump version 2024-04-16 00:15:48 +00:00
Miodrag Milanović e78c38b556
Merge pull request #4339 from YosysHQ/mmicko/lib_as_attribute 
verific: expose library name as module attribute
 2024-04-15 20:25:49 +02:00
Jannis Harder 1527cc84c4
Merge pull request #4338 from jix/fix-formalff-setundef-srst 
formalff -setundef: Fix handling for has_srst FFs
 2024-04-15 18:34:07 +02:00
Miodrag Milanovic af94123730 verific: expose library name as module attribute 2024-04-15 17:01:07 +02:00
Jannis Harder 2bd889a59a formalff -setundef: Fix handling for has_srst FFs 
The `has_srst`` case was checking `sig_ce` instead of `sig_srst` due to
a copy and paste error.

This would crash when `has_ce` was false and could incorrectly determine
that an initial value is unused when `has_ce` and `has_srst` are both
set.
 2024-04-15 11:53:30 +02:00
Miodrag Milanović 7bb2746208
Merge pull request #4334 from YosysHQ/docs_tidy 
Strip compilation date from doc outputs
 2024-04-15 08:27:41 +02:00
Krystine Sherwin 73d021562f
Docs: Rename source/temp to source/generated 2024-04-15 10:13:22 +12:00
Krystine Sherwin 953f5bbe6c
Docs: Remove end-before tag for yosys-abc 2024-04-15 09:50:46 +12:00
Martin Povišer b827b9862f
Merge pull request #4265 from povik/iattr_help 
memory_map: Explain `-iattr` better
 2024-04-13 18:13:58 +02:00
Martin Povišer 4a8cdfabbb
Merge pull request #4169 from povik/clean-opt_clean-step2 
opt_clean: Remove dead assertion
 2024-04-13 18:12:40 +02:00
github-actions[bot] ed46453cfc Bump version 2024-04-13 00:14:07 +00:00
Krystine Sherwin b3024289c6
Docs: Force read_verilog to avoid verific header 2024-04-13 11:33:04 +12:00
Krystine Sherwin 1d7b7ddfd7
Docs: Skip footer in logs 2024-04-13 11:29:11 +12:00
Krystine Sherwin d4b6042e43
Makefile: Separate docs/usage stderr and stdout 2024-04-13 11:20:36 +12:00
Peter Gadfort a48825a604 add support for using ABCs library merging when providing multiple liberty files 2024-04-12 13:57:29 -04:00
N. Engelhardt e8ec19c273 add command that should not have any effect to hierarchy -generate test (this documents the current behavior, not sure if it is desired functionality) 2024-04-12 13:51:06 +02:00
N. Engelhardt b87327d1b9 fix hierarchy -generate mode handling of cells 2024-04-12 13:38:33 +02:00
Miodrag Milanović 1c09862ad9
Merge pull request #4329 from YosysHQ/mmicko/codeowners_change 
Add workflows and CODEOWNERS and fixed gitignore
 2024-04-12 10:46:37 +02:00
Miodrag Milanovic 0c7ac36dcf Add workflows and CODEOWNERS and fixed gitignore 2024-04-11 14:56:00 +02:00
github-actions[bot] 47bdb3e32f Bump version 2024-04-11 00:16:34 +00:00
Emil J c5912f4f95
Merge pull request #4313 from widlarizer/emil/fix-opt-demorgan-warning 
opt_demorgan: fix extra args warning
 2024-04-10 12:49:14 +02:00
Martin Povišer b00abe4a26 Extend `log` command with `-push`, `-pop`, `-header` options 2024-04-10 11:49:20 +02:00
Miodrag Milanovic e2cfcbcf25 fix .gitignore 2024-04-10 10:12:05 +02:00
Miodrag Milanovic e01e942f81 Next dev cycle 2024-04-10 08:21:35 +02:00
Miodrag Milanovic a1bb0255d6 Release version 0.40 2024-04-10 08:17:27 +02:00
N. Engelhardt 3d5e23e585
Merge pull request #4302 from YosysHQ/vhdl_2019 
Verific support for VHDL 2019
 2024-04-09 18:25:05 +02:00
N. Engelhardt 18afa36acd
Merge pull request #4273 from YosysHQ/vhdl_params 
verific: Improve import VHDL constants
 2024-04-09 18:01:41 +02:00
github-actions[bot] bc14999287 Bump version 2024-04-09 00:16:14 +00:00
Jannis Harder eb6c9395bf
Merge pull request #4312 from jix/break-cyclic-includes 
kernel: Avoid including files outside include guards
 2024-04-08 20:49:52 +02:00
Martin Povišer dc746080f5
Merge pull request #4298 from povik/kogge-stone 
techmap: Add a Kogge-Stone option for `$lcu` mapping
 2024-04-08 16:46:06 +02:00
Martin Povišer 5f4d13ee3f techmap: Note down iteration in Kogge-Stone 2024-04-08 16:45:40 +02:00
N. Engelhardt 8e8885e1cc
Merge pull request #4323 from YosysHQ/tests_update 
Tests update for latest more strict iverilog
 2024-04-08 15:10:59 +02:00
Miodrag Milanovic 4ac10040ce Enable SV for localparam use by Efinix cell_sim 2024-04-08 12:45:43 +02:00
Miodrag Milanovic 91e41d8c80 Move parameters to module declaration 2024-04-08 12:44:37 +02:00
KrystalDelusion 32bbca8586
Merge pull request #4316 from widlarizer/emil/document-macc 
docs: Document $macc
 2024-04-08 21:24:25 +12:00
Martin Povišer 47931f9050
Merge pull request #4295 from gadfort/add-ports-stat 
add port statistics to stat command
 2024-04-08 11:12:02 +02:00
Emil J. Tywoniak 43ef916f86 Restructure rst 2024-04-05 14:01:25 +02:00
Emil J. Tywoniak 9510293a94 fixup 2024-04-04 18:16:58 +02:00
github-actions[bot] 22c5ab90d1 Bump version 2024-04-04 00:16:37 +00:00
Emil J. Tywoniak a580a7c82c docs: Document $macc 2024-04-03 20:37:54 +02:00
Catherine d9a4a42389 write_verilog: don't `assign` to a `reg`. 
Fixes #2035.
 2024-04-03 13:06:45 +02:00
Emil J. Tywoniak 4bb3b099d2 opt_demorgan: fix extra args warning 2024-04-03 10:02:53 +02:00
github-actions[bot] 040605b047 Bump version 2024-04-03 00:15:49 +00:00
Jannis Harder d8687e87b1 kernel: Avoid including files outside include guards 
This adjusts the way the headers kernel/{yosys,rtlil,register,log}.h
include each other to avoid the need of including headers outside of
include guards as well as avoiding the inclusion of rtlil.h in the
middle of yosys.h with rtlil.h depending on the prefix of yosys.h, and
the suffix of yosys.h depending on rtlil.h.

To do this I moved some of the declaration in yosys.h into a new header
yosys_common.h. I'm not sure if that is strictly necessary.

Including any of these files still results in the declarations of all
these headers being included, so this shouldn't be a breaking change for
any passes or external plugins.

My main motivation for this is that ccls's (clang based language server)
include guard handling gets confused by the previous way the includes
were done. It often ends up treating the include guard as a generic
disabled preprocessor conditional, breaking navigation and highlighting
for the core RTLIL data structures.

Additionally I think avoiding cyclic includes in the middle of header
files that depend on includes being outside of include guards will also
be less confusing for developers reading the code, not only for tools
like ccls.
 2024-04-02 16:53:56 +02:00
Catherine cb07710162 write_verilog: only warn on processes with sync rules. 
Processes without sync rules correspond to simple decision trees that
directly correspond to `always @*` or `always_comb` blocks in Verilog,
and do not need a warning.

This removes the need to suppress warnings during the RTLIL-to-Verilog
conversion performed by Amaranth.
 2024-04-02 14:48:44 +01:00