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verific: expose library name as module attribute

This commit is contained in:
Miodrag Milanovic 2024-04-15 17:01:07 +02:00
parent 7bb2746208
commit af94123730
1 changed files with 1 additions and 0 deletions
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frontends/verific/verific.cc
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@ -1430,6 +1430,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
}
import_attributes(module->attributes, nl, nl);
module->set_string_attribute(ID::hdlname, nl->CellBaseName());
module->set_string_attribute(ID(library), nl->Owner()->Owner()->Name());
#ifdef VERIFIC_VHDL_SUPPORT
if (nl->IsFromVhdl()) {
NameSpace name_space(0);